Figure 23.24 Synchronous Dram Normal Read Bus Cycle: Pre + Act + Read Commands, Burst (Rcd [1:0] = 01, Tpc [2:0] = 001, Cas Latency = 3) - Hitachi SH7751 Hardware Manual

Figure 23.24 Synchronous DRAM Normal Read Bus Cycle: PRE + ACT + READ
Commands, Burst (RCD [1:0] = 01, TPC [2:0] = 001, CAS Latency = 3)
Rev. 3.0, 04/02, page 979 of 1064