V
H
0.5V
DDQ
Figure 23.70 PCI Clock Input Timing
PCICLK
Output delay
3-state output
t
PCION
Figure 23.71 Output Signal Timing
t
PCICYC
t
t
PCIHIGH
PCILOW
V
H
V
L
t
PCIf
0.4V
DDQ
t
PCIVAL
V
H
0.5V
DDQ
V
L
t
PCIr
0.4V
DDQ
t
PCIOFF
Rev. 3.0, 04/02, page 1025 of 1064