Tc1
Tc2
Tc3 Tc4/Td1
Td2
Td3
Td4
Td5
Td6
Td7
Td8
CKIO
Bank
Precharge-sel
H/L
H/L
c1
c5
Address
RD/
DQMn
D31–D0
c1
c2
c3
c4
c5
c6
c7
c8
(read)
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.29 Burst Read Timing (RAS Down, Same Row Address)
Rev. 3.0, 04/02, page 404 of 1064