T1
CKIO
A25–A5
A4–A0
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
TS1
T1
CKIO
A25–A5
A4–A0
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Tw
Twe
TB2
TB1
Figure 13.42 Burst ROM Wait Access Timing
TB2
TH1
TS1
TB1
Figure 13.43 Burst ROM Wait Access Timing
Tw
TB2
TB1
Tw
TB2
TH1
TS1
TB1
TB2
Rev. 3.0, 04/02, page 421 of 1064
TB2
TB1
Tw
T2
TH1
TS1
TB1
T2
TH1