Peripheral Module Signal Timing; Table 23.28 Peripheral Module Signal Timing (1) - Hitachi SH7751 Hardware Manual

23.3.4

Peripheral Module Signal Timing

Table 23.28 Peripheral Module Signal Timing (1)

Module Item Symbol Min Max
TMU, Timer clock t
RTC pulse width
(high)
Timer clock t
pulse width
(low)
Timer clock t
rise time
Timer clock t
fall time
t
Oscillation
settling time
SCI Input clock t
cycle (asyn-
chronous)
Input clock t
cycle (syn-
chronous)
Input clock t
pulse width
Input clock t
rise time
Input clock t
fall time
Transfer t
data delay
time
Receive t
data setup
time (syn-
chronous)
Receive t
data hold
time (syn-
chronous)
I/O Output data t
ports delay time
Input data t
setup time
Input data t
hold time
HD6417751 HD6417751
RBP240 RBP200
2
*
Min Max
4 — 4
TCLKWH
4 — 4
TCLKWL
— 0.8 —
TCLKr
— 0.8 —
TCLKf
— 3 —
ROSC
4 — 4
Scyc
6 — 6
Scyc
0.4 0.6 0.4
SCKW
— 0.8 —
SCKr
— 0.8 —
SCKf
1.5 5.3 1.5
TXD
16 — 16
RXS
16 — 16
RXH
1.5 5.3 1.5
PORTD
2 — 2.5
PORTS
1.5 — 1.5
PORTH
HD6417751 HD6417751
RF240 RF200
2 2
* *
Min Max Min Max Unit
— 4 — 4
— 4 — 4
0.8 — 0.8 —
0.8 — 0.8 —
3 — 3 —
— 4 — 4
— 6 — 6
0.6 0.4 0.6 0.4
0.8 — 0.8 —
0.8 — 0.8 —
5.3 1.5 6 1.5
— 16 — 16
— 16 — 16
5.3 1.5 6 1.5
— 3.5 — 3.5
— 1.5 — 1.5
Rev. 3.0, 04/02, page 1015 of 1064
2
*
Figure Notes
1
— Pcyc* 23.64
1
— Pcyc* 23.64
1
0.8 Pcyc* 23.64
1
0.8 Pcyc* 23.64
3 s 23.64
1
— Pcyc* 23.64
1
— Pcyc* 23.64
0.6 t 23.64
Scyc
1
0.8 Pcyc* 23.64
1
0.8 Pcyc* 23.64
6 ns 23.64
— ns 23.64
— ns 23.64
6 ns 23.64
— ns 23.64
— ns 23.64