Dma Channel Control Registers 0-3 (Chcr0-Chcr3) - Hitachi SH7751 Hardware Manual

14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)
Bit: 31
SSA2
Initial value: 0
R/W: R/W
Bit: 23
—
Initial value: 0
R/W: R
Bit: 15
DM1
Initial value: 0
R/W: R/W
Bit: 7
TM
Initial value: 0
R/W: R/W
Notes: The TE bit can only be written with 0 after being read as 1, to clear the flag.
The RL, AM, AL, and DS bits may be absent, depending on the channel.
DMA channel control registers 0–3 (CHCR0–CHCR3) are 32-bit readable/writable registers that
specify the operating mode, transfer method, etc., for each channel. Bits 31–28 and 27–24 indicate
the source address and destination address, respectively; these settings are only valid when the
transfer involves the CS5 or CS6 space and the relevant space has been specified as a PCMCIA
interface space. In other cases, these bits should be cleared to 0. For details of the PCMCIA
interface, see section 13.3.7, PCMCIA Interface.
Bits 18 and 16 are not present in CHCR2 and CHCR3. In CHCR2 and CHCR3, these bits cannot
be modified (for write, a write value of 0 should always be used) and are always read as 0.
These registers are initialized to H'00000000 by a power-on or manual reset. They retain their
values in standby mode, sleep mode, and deep sleep mode.
30 29
SSA1 SSA0
0 0
R/W R/W
22 21
— —
0 0
R R
14 13
DM0 SM1
0 0
R/W R/W
6 5
TS2 TS1
0 0
R/W R/W
28 27
STC DSA2 DSA1
0 0
R/W R/W
20 19
— DS
0 —
R R/W (R/W)
12 11
SM0 RS3
0 0
R/W R/W
4 3
TS0 —
0 0
R/W R
Rev. 3.0, 04/02, page 473 of 1064
26 25
DSA0 DTC
0 0
R/W R/W R/W
18 17
RL AM
— —
R/W (R/W)
10 9
RS2 RS1 RS0
0 0
R/W R/W R/W
2 1
IE TE
0 0
R/W R/(W) R/W
24
0
16
AL
—
8
0
0
DE
0