Figure 23.10 Pll Synchronization Settling Time In Case Of Irl Interrupt - Hitachi SH7751 Hardware Manual

Stable input clock
EXTAL input
PLL synchronization
PLL output,
CKIO output
Internal clock
STATUS1–
Normal
STATUS0
Note: When an external clock is input from EXTAL.
Figure 23.9 PLL Synchronization Settling Time in Case of
Stable input clock
EXTAL input
PLL synchronization
PLL output,
CKIO output
Internal clock
STATUS1–
Normal
STATUS0
Note: When an external clock is input from EXTAL.

Figure 23.10 PLL Synchronization Settling Time in Case of IRL Interrupt

Rev. 3.0, 04/02, page 960 of 1064
Reset or NMI
interrupt request
Standby
NMI Interrupt
–
interrupt request
t
IRLSTB
Standby
Stable input clock
× 2
t
PLL synchronization
PLL


 
  


Stable input clock
× 2
PLL synchronization
t
PLL
Normal
or
Normal