Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment
Operation
Access
Size
Address No. D31–D24 D23–D16 D15–D8 D7–D0
Byte
2n
1
2n+1
1
Word
2n
1
Long-
4n
1
word
4n+2
2
Quad-
8n
1
word
8n+2
2
8n+4
3
8n+6
4
Data Bus
—
—
Data
7–0
—
—
—
—
—
Data
15–8
—
—
Data
31–24
—
—
Data
15–8
—
—
Data
63–56
—
—
Data
47–40
—
—
Data
31–24
—
—
Data
15–8
,
,
DQM3
DQM2
—
Data
7–0
Data
7–0
Data
23–16
Data
7–0
Data
55–48
Data
39–32
Data
23–16
Data
7–0
Rev. 3.0, 04/02, page 361 of 1064
Strobe Signals
,
,
,
,
,
DQM1
DQM0
Asserted
Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
Asserted Asserted
,