Figure 13.39 Basic Timing Of A Burst Read From Synchronous Dram (Burst Length = 8) - Hitachi SH7751 Hardware Manual

by the setting of the TPC2 to TPC0 bits of the MCR, and no command that operates on the
synchronous DRAM is issued during these cycles.
Figure 13.39 shows an example of the basic timing of a burst-read. To allow the connection of
a lower-speed DRAM, the cycle's period can be extended by the settings of the bits in WCR2
and MCR. The number of cycles from cycle Tr on which the ACTV command is output to
cycle Tc1 on which the READA command is output can be specified by the RCD1 and RCD0
bits in MCR: the number of cycles is 2, 3, or 4 for the setting value of 1, 2, or 3, respectively.
When two or more cycles are specified, the Trw cycle, which is for the issuing of NOP
commands to the synchronous DRAM, is inserted between the Tr and Tc cycles. The number
of cycles from cycle Tc1 on which the READA command is output until cycle Td1, in which
the first part of the data to be read is received, can be set by the bits A2W2 to A2W0 and
A3W2 to A3W0 of WCR2. These independently select a number of cycles between 1 and 5 for
areas 2 and 3. Note that this number of cycles is equal to the number of CAS latency cycles of
the synchronous DRAM.
Tr Trw
CKIO
Bank Row
Precharge-sel
Row
Address Row
RD/
DQMn
D31–D0
(read)
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.39 Basic Timing of a Burst Read from Synchronous DRAM (Burst Length = 8)

Tc1 Tc2 Tc3 Tc4/Td1
H/L
c1
Td3 Td4
Td2 Td5
c1 c2 c3 c4
Rev. 3.0, 04/02, page 417 of 1064
Td8 Tpc
Td6 Td7
c5 c6 c7 c8