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Philips Semiconductors
2
I
C INTERFACE
2
Table 1: I
C clock rates selection
I2SCLL
+
CRSEL
7.373 MHz
I2SCLH
100
0
150
0
200
0
3.6 - 922 Kbps
-
1
timer1 in mode2
2
I
C operation mode
Master Transmitter Mode
In this mode data is transmitted from master to slave. Before the Master Transmitter Mode can be entered, I2CON must be
initialized as follows:
I2CON (D8h)
CRSEL defines the bit rate. I2EN must be set to 1 to enable the I
slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave
mode. STA, STO, and SI bits must be cleared to 0.
The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the
data direction bit (R/W) will be logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is transmitted, an
acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer.
2
The I
C will enter Master Transmitter Mode by setting the STA bit. The I
bus is free. After the START condition is transmitted, the SI bit is set, and the status code in I2STAT should be 08h. This status
code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT (Data Register)
and data direction bit (SLA+W). The SI bit must be cleared before the data transfer can continue.
When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again,
and the possible status codes are 18h, 20h, or 38h for the master mode or 68h, 78h, or 0B0h if the slave mode was enabled
(setting AA = Logic 1). The appropriate action to be taken for each of these status codes is shown in Table 2.
2003 Dec 8
Bit data rate (Kbit/sec) at f
3.6865 MHz
37
18
25
12
18
9
1.8 - 461 Kbps
timer1 in mode 2
7
6
5
-
I2EN
STA
-
1
0
Figure 10-6: I
OSC
1.8433 MHz
12 MHz
9
60
6
40
5
30
0.9 - 230 Kbps
5.86 - 1500 Kbps
timer1 in mode 2
timer1 in mode 2
4
3
2
STO
SI
AA
0
0
x
2
C Control register
2
C function. If the AA bit is 0, it will not acknowledge its own
2
C logic will send the START condition as soon as the
67
User's Manual - Preliminary -
P89LPC920/921/922
6 MHz
30
20
15
2.93 - 750 Kbps
timer1 in mode 2
1
0
-
CRSEL
-
bit rate
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