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Philips Semiconductors
INTERRUPTS
Table 3-2: Summary of interrupts
Description
External Interrupt 0
Timer 0 Interrupt
External Interrupt 1
Timer 1 Interrupt
1,3
Serial Port Tx and Rx
1,3
Serial Port Rx
Brownout Detect
Watchdog Timer/Real-
time Clock
2
I
C Interrupt
KBI Interrupt
Comparators 1/2 interrupt
2
Serial Port Tx
1. SSTAT.5 = 0 selects combined Serial Port (UART) Tx and Rx interrupt; SSTAT.5 = 1 selects Serial Port Rx interrupt only
(Tx interrupt will be different, see Note 3 below).
2. This interrupt is used as Serial Port (UART) Tx interrupt if and only if SSTAT.5 = 1, and is disabled otherwise.
3. If SSTAT.0 = 1, the following Serial Port additional flag bits can cause this interrupt: FE, BR, OE
The P89LPC920/921/922 has two external interrupt inputs in addition to the Keypad Interrupt function. The two interrupt inputs
are identical to those present on the standard 80C51 microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in
Register TCON. If ITn = 0, external interrupt n is triggered by a low level detected at the INTn pin. If ITn = 1, external interrupt n
is edge triggered. In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next
cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.
Since the external interrupt pins are sampled once each machine cycle, an input high or low level should be held for at least one
machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request
pin high for at least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is
detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.
If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is
generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be
generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.
If an external interrupt is enabled when the P89LPC920/921/922 is put into Power down or Idle mode, the interrupt occurance
will cause the processor to wake up and resume operation. Refer to the section on Power Reduction Modes for details.
External Interrupt pin glitch suppression
Most of the P89LPC920/921/922 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC920/
921/922 datasheet, AC Electrical Characteristics for glitch filter specifications) . However, pins SDA/INT0/P1.3 and SCL/T0/P1.2
do not have the glitch suppression circuits. Therefore, INT1 has glitch suppression while INT0 does not.
2003 Dec 8
Interrupt
Vector
flag bit(s)
address
IE0
0003h
TF0
000Bh
IE1
0013h
TF1
001Bh
TI & RI
0023h
RI
BOF
002Bh
WDOVF/
0053h
RTCF
SI
0033h
KBIF
003Bh
CMF1/CMF2
0043h
TI
006Bh
Interrupt
Interrupt
enable bit(s)
priority
EX0 (IEN0.0)
IP0H.0, IP0.0
ET0 (IEN0.1)
IP0H.1, IP0.1
EX1 (IEN0.2)
IP0H.2, IP0.2
ET1 (IEN0.3)
IP0H.3, IP0.3
ES/ESR
IP0H.4, IP0.4
(IEN0.4)
EBO (IEN0.5)
IP0H.5, IP0.5
EWDRT
IP0H.6, IP0.6
(IEN0.6)
EI2C (IEN1.0)
IP1H.0, IP1.0
EKBI (IEN1.1)
IP1H.1, IP1.1
EC (IEN1.2)
IP1H.2, IP1.2
EST (IEN1.6)
P1H.6, IP1.6
26
User's Manual - Preliminary -
P89LPC920/921/922
Arbitration
Power down
ranking
wakeup
1 (highest)
Yes
4
No
6
Yes
8
No
11
No
2
Yes
3
Yes
5
No
7
Yes
9
Yes
10
No
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