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Philips Semiconductors
ANALOG COMPARATORS
11. ANALOG COMPARATORS
Two analog comparators are provided on the P89LPC920/921/922. Input and output options allow use of the comparators in a
number of different configurations. Comparator operation is such that the output is a logical one (which may be read in a register
and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a
pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt
when the output value changes.
Comparator configuration
Each comparator has a control register, CMP1 for comparator 1 and CMP2 for comparator 2. The control registers are identical
and are shown in Figure 11-1.
The overall connections to both comparators are shown in Figure 11-2. There are eight possible configurations for each
comparator, as determined by the control bits in the corresponding CMPn register: CPn, CNn, and OEn. These configurations
are shown in Figure 11-3.
When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10
microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag
must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.
CMPn
Address: ACh (CMP1), ADh (CMP2)
Not bit addressable
Reset Source(s): Any reset
Reset Value: xx000000B
BIT
SYMBOL
CMPn.7, 6
-
CMPn.5
CEn
CMPn.4
CPn
CMPn.3
CNn
CMPn.2
OEn
CMPn.1
COn
CMPn.0
CMFn
2003 Dec 8
7
6
-
-
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Comparator enable. When set, the corresponding comparator function is enabled.
Comparator output is stable 10 microseconds after CEn is set.
Comparator positive input select. When 0, CINnA is selected as the positive comparator
input. When 1, CINnB is selected as the positive comparator input.
Comparator negative input select. When 0, the comparator reference pin CMPREF is
selected as the negative comparator input. When 1, the internal comparator reference,
Vref, is selected as the negative comparator input.
Output enable. When 1, the comparator output is connected to the CMPn pin if the
comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock.
Comparator output, synchronized to the CPU clock to allow reading by software.
Comparator interrupt flag. This bit is set by hardware whenever the comparator output
COn changes state. This bit will cause a hardware interrupt if enabled. Cleared by
software.
Figure 11-1: Comparator control registers (CMP1 and CMP2)
5
4
3
CEn
CPn
CNn
79
User's Manual - Preliminary -
P89LPC920/921/922
2
1
0
OEn
COn
CMFn
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