Internal Reference Voltage; Comparator Interrupt; Comparators And Power Reduction Modes - Philips P89LPC920 User Manual

Philips Semiconductors
ANALOG COMPARATORS
(P0.4) CIN1A
(P0.3) CIN1B
(P0.5) CMPREF
Vref
(P0.2) CIN2A
(P0.1) CIN2B

Internal reference voltage

An internal reference voltage, Vref, may supply a default reference when a single comparator input pin is used. Please refer to
the Datasheet for specifications.

Comparator interrupt

Each comparator has an interrupt flag CMFn contained in its configuration register. This flag is set whenever the comparator
output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one
common interrupt vector. The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the
interrupt system is enabled via the EA bit in the IEN0 register. If both comparators enable interrupts, after entering the interrupt
service routine, the user will need to read the flags to determine which comparator caused the interrupt.
When a comparator is disabled the comparator's output, COx, goes high. If the comparator output was low and then is disabled,
the resulting transition of the comparator output from a low to high state will set the the comparator flag, CMFx. This will cause
an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling
the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator.

Comparators and power reduction modes

Either or both comparators may remain enabled when Power down or Idle mode is activated, but both comparators are disabled
automatically in Total Power down mode.
If a comparator interrupt is enabled (except in Total Power down mode), a change of the comparator output state will generate
an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-
pull mode in order to obtain fast switching times while in Power down mode. The reason is that with the oscillator stopped, the
temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.
2003 Dec 8
CP1
Comparator 1
+
-
CN1
CP2
Comparator 2
+
-
CN2
Figure 11-2: Comparator input and output connections
OE1
CO1
Change Detect
CMF1
Change Detect
CMF2
CO2
OE2
80
User's Manual - Preliminary -
P89LPC920/921/922
CMP1 (P0.6)
Interrupt
EC
CMP2 (P0.0)