Timers 0 And 1 - Philips P89LPC920 User Manual

Philips Semiconductors

TIMERS 0 AND 1

7. TIMERS 0 AND 1
The P89LPC920/921/922 has two general-purpose counter/timers which are upward compatible with the 80C51 Timer 0 and
Timer 1. Both can be configured to operate either as timers or event counters (see Figure 7-1). An option to automatically toggle
the Tx pin upon timer overflow has been added.
In the "Timer" function, the timer is incremented every PCLK.
In the "Counter" function, the register is incremented in response to a 1-to-0 transition on its corresponding external input pin (T0
or T1). The external input is sampled once during every machine cycle. When the pin is high during one cycle and low in the next
cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the
transition was detected. Since it takes 2 machine cycles (4 CPU clocks) to recognize a 1-to-0 transition, the maximum count rate
is 1/4 of the CPU clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a
given level is sampled at least once before it changes, it should be held for at least one full machine cycle.
The "Timer" or "Counter" function is selected by control bits TnC/T (x = 0 and 1 for Timers 0 and 1 respectively) in the Special
Function Register TMOD. Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6), which are selected by bit-
pairs (TnM1, TnM0) in TMOD and TnM2 in TAMOD. Modes 0, 1, 2 and 6 are the same for both Timers/Counters. Mode 3 is
different. The operating modes are described later in this section.
TMOD
Address: 89h
Not bit addressable
Reset Source(s): Any source
Reset Value: 00000000B
BIT SYMBOL
TMOD.7 T1GATE
TMOD.6 T1C/T
TMOD.5, 4 T1M1,T1M0
TMOD.3 T0GATE
TMOD.2 T0C/T
TMOD.1, 0 T0M1,T0M0
2003 Dec 8
7 6
T1GATE T1C/T
FUNCTION
Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is
high and the TR1 control pin is set. When cleared, Timer 1 is enabled when the TR1
control bit is set.
Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from CCLK). Set
for Counter operation (input from T1 input pin).
Mode Select for Timer 1.These bits are used with the T1M2 bit in the TAMOD register to
determine the Timer 1 mode (see Figure 7-2).
Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0 pin is
high and the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0
control bit is set.
Timer or Counter Selector for Timer 0. Cleared for Timer operation (input from CCLK). Set
for Counter operation (input from T0 input pin).
Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to
determine the Timer 0 mode (see Figure 7-2).
Figure 7-1: Timer/Counter Mode Control register (TMOD)
5 4 3
T1M1 T1M0 T0GATE
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User's Manual - Preliminary -
P89LPC920/921/922
2 1 0
T0C/T T0M1 T0M0