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Fig 8. ADC block diagram.
3.2.1 A/D operating modes
3.2.1.1 Fixed channel, single conversion mode
A single input channel can be selected for conversion. A single conversion will be
performed and the result placed in the result register pair which corresponds to the
selected input channel (see
conversion completes. The input channel is selected in the ADINS register. This mode is
selected by setting the SCAN0 bit in the ADMODA register.
Table 7:
Result register
AD0DAT0R/L
User manual
– Fixed channel, single conversion mode
– Fixed channel, continuous conversion mode
– Auto scan, single conversion mode
– Auto scan, continuous conversion mode
– Dual channel, continuous conversion mode
– Single step mode
•
Three conversion start modes
– Timer triggered start
– Start immediately
– Edge triggered
10-bit conversion time of 4 µs at an A/D clock of 9 MHz
•
•
Interrupt or polled operation
•
High and low boundary limits interrupt
•
Clock divider
•
Power down mode
INPUT
MUX
Input channels and result registers for fixed channel single, auto scan single, and
auto scan continuous conversion modes
Input channel
AD00
Rev. 03 — 7 June 2005
comp
+
–
DAC1
Table
7). An interrupt, if enabled, will be generated after the
Result register
AD0DAT4R/L
UM10119
P89LPC938 User manual
SAR
CONTROL
LOGIC
8
CCLK
002aab103
Input channel
AD04
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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