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Philips Semiconductors
CLOCKS
2. CLOCKS
Enhanced CPU
The P89LPC920/921/922 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine
cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.
Clocks
Clock definitions
The P89LPC920/921/922 device has several internal clocks as defined below:
• OSCCLK - Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources (see Figure 2-3) and can also
be optionally divided to a slower frequency (see section "CPU Clock (CCLK) modification: DIVM register").
Note: f
is defined as the OSCCLK frequency.
OSC
• CCLK - CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are
executed in one to two machine cycles (two or four CCLK cycles).
• RCCLK - The internal 7.373 MHz RC oscillator output.
• PCLK - Clock for the various peripheral devices and is CCLK/2.
Oscillator clock (OSCCLK)
The P89LPC920/921/922 provides several user-selectable oscillator options. This allows optimization for a range of needs from
high precision to lowest possible cost. These options are configured when the FLASH is programmed and include an on-chip
watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source. The crystal
oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 12 MHz.
Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this
configuration.
Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this
configuration.
High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 12 MHz. Ceramic resonators are also supported in this
configuration.
Clock output
The P89LPC920/921/922 supports a user-selectable clock output function on the XTAL2 / CLKOUT pin when the crystal
oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator,watchdog
oscillator, external clock input on X1) and if the Real-time Clock is not using the crystal oscillator as its clock source. This allows
external devices to synchronize to the P89LPC920/921/922. This output is enabled by the ENCLK bit in the TRIM register
The frequency of this clock output is 1/2 that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior
to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value.
2003 Dec 8
21
User's Manual - Preliminary -
P89LPC920/921/922
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