I2C Interface - Philips P89LPC920 User Manual

Philips Semiconductors
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I C INTERFACE
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10. I C INTERFACE
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The I C-bus uses two wires, serial clock (SCL) and serial data (SDA) to transfer information between devices connected to the
bus, and has the following features:
• Bidirectional data transfer between masters and slaves
• Multimaster bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
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• The I C-bus may be used for test and diagnostic purposes
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A typical I C-bus configuration is shown in Figure 1. Depending on the state of the direction bit (R/W), two types of data transfers
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are possible on the I C-bus:
• Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next
follows a number of data bytes. The slave returns an acknowledge bit after each received byte.
• Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The
slave then returns an acknowledge bit. Next follows the data bytes transmitted by the slave to the master. The master returns
an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge"
is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended
with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the
next serial transfer, the I
The P89LPC920/921/922 device provides a byte-oriented I
Master Receiver Mode, Slave Transmitter Mode and Slave Receiver Mode.
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I C-bus
P1.3/SDA P1.2/SCL
P89LPC920/921/922
The P89LPC920/921/922 CPU interfaces with the I
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Register), I2DAT (I C Data Register), I2STAT (I
Cycle Register High Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).
2003 Dec 8
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C-bus will not be released.
Other Device with I
Figure 1: I
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C-bus through six Special Function Registers (SFRs): I2CON (I
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C Status Register), I2ADR (I
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C interface. It has four operation modes: Master Transmitter Mode,
R R
P P
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C
Interface
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C-bus configuration
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C Slave Address Register), I2SCLH (SCL Duty
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User's Manual - Preliminary -
P89LPC920/921/922
SDA
SCL
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Other Device with I C
Interface
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C Control