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Philips Semiconductors
User's Manual - Preliminary -
P89LPC920/921/922
CLOCKS
can allow bypassing the oscillator start-up time in cases where Power down mode would otherwise be used. The value of DIVM
may be changed by the program at any time without interrupting code execution.
Low power select
The P89LPC920/921/922 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is 8 MHz or slower, the CLKLP
SFR bit (AUXR1.7) can be set to a '1' to lower the power consumption further. On any reset, CLKLP is '0' allowing highest
performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.
24
2003 Dec 8
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