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Philips Semiconductors
UART
Register
SSTAT
Serial Port (UART) Status
BRGR1
Baud Rate Generator Rate High Byte
BRGR0
Baud Rate Generator Rate Low Byte
BRGCON
Baud Rate Generator Control
Baud Rate Generator and selection
The P89LPC920/921/922 enhanced UART has an independent Baud Rate Generator. The baud rate is determined by a value
programmed into the BRGR1 and BRGR0 SFRs. The UART can use either Timer 1 or the baud rate generator output as
determined by BRGCON.2-1 (see Figure 9-2). Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is set. The
independent Baud Rate Generator uses CCLK.
Updating the BRGR1 and BRGR0 SFRs
The baud rate SFRs, BRGR1 and BRGR0 must only be loaded when the Baud Rate Generator is disabled (the BRGEN bit in
the BRGCON register is '0'). This avoids the loading of an interim value to the baud rate generator. (CAUTION: If either BRGR0
or BRGR1 is written when BRGEN = 1, the result is unpredictable.)
Table 9-2: Baud rate generation for UART
SCON.7
SCON.6
(SM0)
(SM1)
0
0
0
1
1
0
1
1
2003 Dec 8
Description
PCON.7
BRGCON.1
(SMOD1)
(SBRGS)
X
X
0
0
1
0
X
1
0
X
1
X
0
0
1
0
X
1
SFR Location
BAH
BFH
BEH
BDH
Receive/transmit baud rate for UART
CCLK/16
CCLK/(256-TH1)64
CCLK/(256-TH1)32
CCLK/((BRGR1,BRGR0)+16)
CCLK/32
CCLK/16
CCLK/(256-TH1)64
CCLK/(256-TH1)32
CCLK/((BRGR1,BRGR0)+16)
52
User's Manual - Preliminary -
P89LPC920/921/922
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