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P89LPC922
Philips P89LPC922 Manuals
Manuals and User Guides for Philips P89LPC922. We have
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Philips P89LPC922 manual available for free PDF download: User Manual
Philips P89LPC922 User Manual (124 pages)
80C51 8-bit microcontroller with two-clock core
Brand:
Philips
| Category:
Microcontrollers
| Size: 1.29 MB
Table of Contents
Table of Contents
3
General Description
9
Pin Configuration
9
20-Pin TSSOP, DIP Package
9
Logic Symbol
9
Pin Descriptions
11
Special Function Registers
14
Memory Organization
18
P89LPC920/921/922 Memory Map
18
Data RAM Arrangement
19
Clocks
21
Enhanced CPU
21
Clock Definitions
21
Oscillator Clock (OSCCLK)
21
Low Speed Oscillator Option
21
Medium Speed Oscillator Option
21
High Speed Oscillator Option
21
Clock Output
21
On-Chip RC Oscillator Option
22
Watchdog Oscillator Option
22
On-Chip RC Oscillator TRIM Register
22
External Clock Input Option
23
Oscillator Clock (OSCCLK) Wakeup Delay
23
CPU Clock (CCLK) Modification: DIVM Register
23
Block Diagram of Oscillator Control
23
Low Power Select
24
Interrupts
25
Interrupt Priority Structure
25
Interrupt Priority Level
25
External Interrupt Pin Glitch Suppression
26
Interrupt Sources, Interrupt Enables, and Power down Wake-Up Sources
27
I/O Ports
29
Port Configurations
29
Quasi-Bidirectional Output Configuration
29
Number of I/O Pins Available
29
Port Output Configuration Settings
29
Open Drain Output Configuration
30
Quasi-Bidirectional Output
30
Open Drain Output
30
Input-Only Configuration
31
Push-Pull Output Configuration
31
Port 0 Analog Functions
31
Input -Only
31
Push-Pull Output
31
Additional Port Features
32
Port Output Configuration
32
Power Monitoring Functions
33
Brownout Detection
33
Power-On Detection
34
Power Reduction Modes
34
Power Reduction Modes
35
Power Control Register (PCON)
36
Power Control Register a (PCONA)
37
Reset
39
Block Diagram of Reset
39
Reset Vector
40
Timers 0 and 1
41
Mode 0
42
Mode 1
42
Mode 2
43
Mode 3
43
Mode 6
43
Timer/Counter 0 or 1 in Mode 0 (13-Bit Counter)
44
Timer/Counter 0 or 1 in Mode 1 (16-Bit Counter)
45
Timer/Counter 0 or 1 in Mode 2 (8-Bit Auto-Reload)
45
Timer Overflow Toggle Output
46
Timer/Counter 0 or 1 in Mode 6 (PWM Auto-Reload)
46
Real-Time Clock/System Timer
47
Real-Time Clock Source
47
Changing RTCS1-0
47
Real-Time Clock/System Timer Block Diagram
47
Real-Time Clock Interrupt/Wake up
48
Reset Sources Affecting the Real-Time Clock
48
Real-Time Clock/System Timer Clock Sources
48
Uart
51
Mode 0
51
Mode 1
51
Mode 2
51
Mode 3
51
SFR Space
51
Baud Rate Generator and Selection
52
Updating the BRGR1 and BRGR0 Sfrs
52
Baud Rate Generation for UART
52
Framing Error
53
Break Detect
53
Baud Rate Generation for UART (Modes 1, 3)
53
More about UART Mode 0
55
More about UART Mode 1
56
Serial Port Mode 0 (Double Buffering Must be Disabled)
56
Serial Port Mode 1 (Only Single Transmit Buffering Case Is Shown)
56
More about UART Modes 2 and 3
57
Framing Error and RI in Modes 2 and 3 with SM2 = 1
57
Break Detect
57
Serial Port Mode 2 or 3 (Only Single Transmit Buffering Case Is Shown)
57
Double Buffering
58
Double Buffering in Different Modes
58
Transmit Interrupts with Double Buffering Enabled (Modes 1, 2 and 3)
58
The 9Th Bit (Bit 8) in Double Buffering (Modes 1, 2 and 3)
59
Multiprocessor Communications
60
Automatic Address Recognition
60
I2C Interface
63
I2C Data Register
64
I2C Slave Address Register
64
I2C Control Register
64
I2C Status Register
66
I2C SCL Duty Cycle Registers I2SCLH and I2SCLL
66
I2C Operation Mode
67
Master Transmitter Mode
67
Master Receiver Mode
68
Slave Receiver Mode
69
Slave Transmitter Mode
69
Master Transmitter Mode
72
Master Receiver Mode
73
Slave Receiver Mode
74
Slave Transmitter Mode
77
Analog Comparators
79
Comparator Configuration
79
Internal Reference Voltage
80
Comparator Interrupt
80
Comparators and Power Reduction Modes
80
Comparator Configuration Example
81
Comparator Configurations
81
Keypad Interrupt (KBI)
83
Keypad Interrupt Mask Register (KBM)
84
13. Watchdog Timer
85
Watchdog Function
85
Watchdog Timer Configuration
85
Feed Sequence
86
Watchdog Timer Control Register
87
Watchdog Clock Source
88
P89LPC920/921/922 Watchdog Timeout Values
88
Watchdog Timer in Timer Mode
89
Watchdog Timer in Watchdog Mode (WDTE = 1)
89
Power down Operation
90
Periodic Wakeup from Power down Without an External Oscillator
90
Watchdog Timer in Timer Mode (WDTE = 0)
90
Additional Features
91
Software Reset
91
Dual Data Pointers
91
AUXR1 Register
91
15. Flash Memory
93
General Description
93
Features
93
Flash Programming and Erase
93
Using Flash as Data Storage: IAP-Lite
93
In-Circuit Programming (ICP)
97
ISP and IAP Capabilities of the P89LPC920/921/922
97
Boot ROM
98
Power-On Reset Code Execution
98
Hardware Activation of the Boot Loader
98
In-System Programming (ISP)
99
Using the In-System Programming
99
In-System Programming (ISP) Hex Record Formats
100
In-Application Programming Method
104
IAP Authorization Key
104
IAP Function Calls
105
User Configuration Bytes
109
User Security Bytes
110
Boot Vector
111
Boot Status
111
16. Instruction Set
113
Instruction Set Summary
113
17. Revision History
117
18. Index
119
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