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5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the interrupt controller.
NMI
input
IRQ input
OVF
TME
.
.
.
.
.
.
.
.
.
.
ADI
ADIE
Legend
I:
Interrupt mask bit
IER:
IRQ enable register
Interrupt priority register A
IPRA:
IPRB:
Interrupt priority register B
ISCR:
IRQ sense control register
ISR:
IRQ status register
SYSCR:
System control register
UE:
User bit enable
UI:
User bit/interrupt mask bit
82
ISCR
IER
IRQ input
section ISR
Interrupt controller
Figure 5-1 Interrupt Controller Block Diagram
IPRA, IPRB
Interrupt
request
Priority
decision logic
Vector
number
SYSCR
CPU
I
CCR
UI
UE
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