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Therefore, to prevent such erroneous operation, operation must be carried out correctly in
according with the program/erase algorithms in the state that flash write enable (FWE) is set. In
addition, the operation must be always carried out correctly by supervising microcomputer errors
inside and outside the chip with the watchdog timer, etc. At transition to this protection mode, the
flash memory may be erroneously programmed or erased, or its abort may result in incomplete
programming and erasing. In such cases, always forcibly return (reprogram) by boot mode.
However, overprogramming and overerasing may prevent the boot mode from starting normally.
15.6.4
NMI Input Disable Conditions
While flash memory is being programed/erased and the boot program is executing in the boot
mode (however, period up to branching to on-chip RAM area)*
the programming/erasing operations have priority.
This is done to avoid the following operation states:
1. Generation of an NMI input during programming/erasing violates the program/erase
algorithms and normal operation can not longer be assured.
2. Vector-read cannot be carried out normally*
programming/erasing and the microcomputer runs away as a result.
3. If an NMI input is generated during boot program execution, the normal boot mode sequence
cannot be executed.
Therefore, this LSI has conditions that exceptionally disable NMI inputs only in the on-board
programming mode. However, this does not assure normal programming/erasing and
microcomputer operation.
Thus, in the FWE application state, all requests, including NMI, inside and outside the
microcomputer, exception handling, and bus release must be restricted. NMI inputs are also
disabled in the error protection state and the state that holds the P or E bit in FLMCR during flash
memory emulation by RAM.
Notes: 1. Indicates the period up to branching to the on-chip RAM boot program area (H'FEF10
to H'FF2FF). (This branch occurs immediately after user program transfer was
completed.)
Therefore, after branching to RAM area, NMI input is enabled in states other than the
program/erase state. Thus, interrupt requests inside and outside the microcomputer
must be disabled until initial writing by user program (writing of vector table and NMI
processing program, etc.) is completed.
2. In this case, vector read is not performed normally for the following two reasons:
a. The correct value cannot be read even by reading the flash memory during
programming/erasing. (Value is undefined.)
1
, NMI input is disabled because
2
during NMI exception handling during
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