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TCR0—Timer Control Register 0
Bit
Initial value
Read/Write
7
6
—
CCLR1
CCLR0
1
0
—
R/W
R/W
Timer prescaler 2 to 0
Bit 2
TPSC2
TPSC1
0
1
Clock edge 1 and 0
Bit 4
Bit 3
CKEG1 CKEG0
0
0
1
1
—
Counter clear 1 and 0
Bit 6
Bit 5
CCLR1 CCLR0
TCNT Clear Source
0
0
TCNT is not cleared
1
TCNT is cleared by GRA compare match or input capture
1
0
TCNT is cleared by GRB compare match or input capture
1
Synchronous clear:
5
4
CKEG1
CKEG0
0
0
R/W
R/W
Bit 1
Bit 0
TPSC0
TCNT Clock Source
0
0
Internal clock: ø
1
Internal clock: ø/2
1
0
Internal clock: ø/4
1
Internal clock: ø/8
0
0
External clock A: TCLKA input
1
External clock B: TCLKB input
1
0
External clock C: TCLKC input
1
External clock D: TCLKD input
Counted Edges of External Clock
Rising edges counted
Falling edges counted
Both edges counted
TCNT is cleared in synchronization
with other synchronized timers
H'64
3
2
TPSC2
TPSC1
0
0
R/W
R/W
ITU0
1
0
TPSC0
0
0
R/W
607
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