18.3.2 Control Signal Timing
Control signal timing is shown as follows:
• Reset input timing
Figure 18-10 shows the reset input timing.
• Reset output timing
Figure 18-11 shows the reset output timing.
• Interrupt input timing
Figure 18-12 shows the interrupt input timing for NMI and IRQ
ø
RES
MD2 to MD0
FWE*
Note:
* The FWE input timing shown is for entering and exiting boot mode.
ø
RESO*
* Flash version does not have RESO output pin
t
RESS
t
MDS
Figure 18-10 Reset Input Timing
t
RESD
Figure 18-11 Reset Output Timing
, IRQ
, IRQ
5
4
t
RESS
t
RESW
t
RESD
t
RESOW
, and IRQ
.
1
0
555