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H'00000
H'1FFFF
H'20000
H'3FFFF
H'40000
H'47FFF
H'48000
H'5FFFF
H'60000
H'6FFFF
H'70000
H'7FFFF
H'E0000
H'E7FFF
H'FFFFF
Note:
The bus width and the number of access states of the on-chip memories and I/O registers
are fixed; they cannot be changed by register setting.
128
On-chip ROM
EPROM
Not used
SRAM1, 2
Not used
SRAM3
Not used
On-chip RAM
On-chip I/O registers
Figure 6-10 Memory Map (H8/3039 Mode 5)
Area 0
Area 1
Area 2
8-bit, three-state-access area
Area 3
8-bit, two-state-access area
Areas 4, 5, 6
Area 7
8-bit, three-state-access area
(one auto-wait state)
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