Hitachi H8/3937 Series Manuals

Manuals and User Guides for Hitachi H8/3937 Series. We have 1 Hitachi H8/3937 Series manual available for free PDF download: Hardware Manual

Hitachi H8/3937 Series Hardware Manual

Hitachi H8/3937 Series Hardware Manual (521 pages)

Brand: Hitachi | Category: Computer Hardware | Size: 2.34 MB

Table of Contents

Table of Contents
5
Overview

13
- Internal Block Diagram
  17
- Pin Arrangement and Functions
  18
  - Pin Arrangement
    18
  - Pin Functions
    19
Cpu

25
- Overview
  25
  - Features
    25
  - Address Space
    26
  - Register Configuration
    26
- Register Descriptions
  27
  - General Registers
    27
  - Control Registers
    27
  - Initial Register Values
    28
- Data Formats
  29
  - Data Formats in General Registers
    30
  - Memory Data Formats
    31
- Addressing Modes
  32
  - Effective Address Calculation
    34
- Instruction Set
  38
  - Data Transfer Instructions
    40
  - Arithmetic Operations
    42
  - Logic Operations
    43
  - Shift Operations
    43
  - Bit Manipulations
    45
  - Branching Instructions
    49
  - System Control Instructions
    51
  - Block Data Transfer Instruction
    52
- Basic Operational Timing
  54
  - Access to On-Chip Memory (RAM, ROM)
    54
  - Access to On-Chip Peripheral Modules
    55
- CPU States
  57
  - Overview
    57
  - Program Execution State
    58
  - Program Halt State
    58
  - Exception-Handling State
    58
- Memory Map
  59
- Application Notes
  62
Exception Handling

71
- Overview
  71
- Reset
  71
  - Reset Sequence
    71
  - Interrupt Immediately after Reset
    72
- Interrupts
  73
  - Overview
    73
  - Interrupt Control Registers
    75
  - External Interrupts
    84
  - Internal Interrupts
    85
  - 3.3.5 Interrupt Operations
    86
  - Interrupt Response Time
    91
- Application Notes
  92
Clock Pulse Generators

97
- Overview
  97
  - Block Diagram
    97
  - System Clock and Subclock
    97
- System Clock Generator
  98
- Subclock Generator
  101
- Prescalers
  103
- Note on Oscillators
  104
  - Definition of Oscillation Settling Standby Time
    104
  - Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator Element)
    106
Power-Down Modes

107
- Overview
  107
  - System Control Registers
    110
- Sleep Mode
  115
  - Transition to Sleep Mode
    115
  - Clearing Sleep Mode
    115
  - Clock Frequency in Sleep (Medium-Speed) Mode
    116
- Standby Mode
  117
- Watch Mode
  121
- Subsleep Mode
  122
  - Transition to Subsleep Mode
    122
  - Clearing Subsleep Mode
    122
- Subactive Mode
  123
  - Transition to Subactive Mode
    123
  - Clearing Subactive Mode
    123
  - Operating Frequency in Subactive Mode
    123
- Active (Medium-Speed) Mode
  124
- Direct Transfer
  125
- Module Standby Mode
  129
  - Setting Module Standby Mode
    129
  - Clearing Module Standby Mode
    129
Rom

131
- Overview
  131
  - Block Diagram
    131
- PROM Mode
  132
  - Setting to PROM Mode
    132
  - Socket Adapter Pin Arrangement and Memory Map
    132
- Programming
  135
  - Writing and Verifying
    135
  - Programming Precautions
    140
- Reliability of Programmed Data
  141
Ram

143
- Overview
  143
  - 7.1.1 Block Diagram
    143
I/O Ports

145
- Overview
  145
- Port 1
  147
  - Overview
    147
  - Register Configuration and Description
    147
  - Pin Functions
    152
  - Pin States
    154
  - MOS Input Pull-Up
    154
- Port 2 [Chip Internal I/O Port]
  155
  - Overview
    155
  - Register Configuration and Description
    155
  - Function
    159
  - States
    159
- Port 3
  160
  - Overview
    160
  - Register Configuration and Description
    160
  - Pin Functions
    163
  - Pin States
    165
  - MOS Input Pull-Up
    165
- Port 4
  166
  - Overview
    166
  - Register Configuration and Description
    166
  - Pin Functions
    168
  - Pin States
    169
- Port 5
  170
  - Overview
    170
  - Register Configuration and Description
    170
  - Pin Functions
    172
  - Pin States
    173
  - MOS Input Pull-Up
    173
- Port 6
  174
  - Overview
    174
  - Register Configuration and Description
    174
  - Pin Functions
    176
  - Pin States
    176
  - MOS Input Pull-Up
    176
- Port 7
  177
  - Overview
    177
  - Register Configuration and Description
    177
  - Pin Functions
    179
  - Pin States
    179
- Port 8
  180
  - Overview
    180
  - Register Configuration and Description
    180
  - Pin Functions
    181
  - Pin States
    181
- Port 9
  182
  - Overview
    182
  - Register Configuration and Description
    182
  - Pin Functions
    184
  - Pin States
    184
- Port a
  185
  - Overview
    185
  - Register Configuration and Description
    185
  - Pin States
    186
- Port B
  187
  - Overview
    187
  - Register Configuration and Description
    187
- Input/Output Data Inversion Function
  188
- Application Note
  190
  - The Management of the Un-Use Terminal
    190
Timers

191
- Overview
  191
- Timer a
  192
  - Overview
    192
  - Register Descriptions
    194
  - Timer Operation
    198
  - Timer a Operation States
    199
  - Application Note
    199
- Timer C
  200
  - Overview
    200
  - Register Descriptions
    202
  - Timer Operation
    205
  - Timer C Operation States
    207
- Timer F
  208
  - Overview
    208
  - Register Descriptions
    211
  - CPU Interface
    218
  - Operation
    221
  - Application Notes
    224
- Timer G
  227
  - Overview
    227
  - Register Descriptions
    229
  - Noise Canceler
    233
  - Operation
    235
  - Application Notes
    239
  - Timer G Application Example
    244
- Watchdog Timer
  245
  - Overview
    245
  - Register Descriptions
    246
  - Timer Operation
    250
  - Watchdog Timer Operation States
    251
Section 10 Serial Communication Interface

253
- Overview
  253
- SCI1 [Chip Internal Function]
  254
  - Overview
    254
  - Register Descriptions
    256
  - Operation
    262
  - Interrupt Source
    264
  - Application Note
    265
- Sci3
  266
  - Overview
    266
  - Register Descriptions
    270
  - Operation
    292
  - Interrupts
    320
  - Application Notes
    321
Section 11 A/D Converter

327
- Overview
  327
  - Features
    327
  - Block Diagram
    328
  - Pin Configuration
    329
  - Register Configuration
    329
- Register Descriptions
  330
  - A/D Result Registers (ADRRH, ADRRL)
    330
  - A/D Mode Register (AMR)
    330
  - A/D Start Register (ADSR)
    332
  - Clock Stop Register 1 (CKSTPR1)
    333
- Operation
  334
- Interrupts
  335
- Typical Use
  335
- Application Notes
  339
Section 12 FLEX Roaming Decoder

341
- Overview
  341
  - Features
    341
  - System Block Diagram
    342
  - 12.1.3 Functional Block Diagram
    344
- SPI Packets
  345
- Host-To-Decoder Packet Descriptions
  350
  - Checksum Packet
    350
  - Configuration Packet
    353
  - Control Packet
    356
  - All Frame Mode Packet
    357
  - Operator Messaging Address Enable Packet
    359
  - Roaming Control Packet
    359
  - Timing Control Packet
    362
  - Receiver Line Control Packet
    363
  - Receiver Control Configuration Packets
    363
  - 12.3.10 Frame Assignment Packets
    367
  - 12.3.11 User Address Enable Packet
    368
  - User Address Assignment Packets
    369
- Decoder-To-Host Packet Descriptions
  370
  - Block Information Word Packet
    371
  - Address Packet
    372
  - Vector Packet
    373
  - Message Packet
    378
  - Roaming Status Packet
    378
  - Receiver Shutdown Packet
    381
  - Status Packet
    382
  - Part ID Packet
    384
- Application Notes
  386
  - Receiver Control
    386
  - Message Building
    389
  - Building a Fragmented Message
    391
  - Operation of a Temporary Address
    394
  - Using the Receiver Shutdown Packet
    396
- Timing Diagrams (Reference Data)
  399
  - SPI Timing
    399
  - Start-Up Timing
    401
  - Reset Timing
    402
Section 13 Electrical Characteristics

403
- Absolute Maximum Ratings
  403
- Electrical Characteristics
  404
  - Power Supply Voltage and Operating Range
    404
  - DC Characteristics
    406
  - AC Characteristics
    410
  - A/D Converter Characteristics
    413
- Operation Timing
  414
- Output Load Circuit
  417
- Resonator Equivalent Circuit
  417
- Usage Note
  418
Appendix A CPU Instruction Set

419
- Instructions
  419
- Operation Code Map
  427
- Number of Execution States
  429
Appendix B Internal I/O Registers

435
- Addresses
  435
- Functions
  438
Appendix C I/O Port Block Diagrams

490
- Block Diagrams of Port 1
  490
- Block Diagrams of Port 2 [Chip Internal I/O Port]
  494
- Block Diagrams of Port 3
  498
- Block Diagrams of Port 4
  505
- Block Diagram of Port 5
  509
- Block Diagram of Port 6
  510
- Block Diagram of Port 7
  511
- Block Diagrams of Port 8
  512
- Block Diagram of Port 9
  513
- Block Diagram of Port a
  514
- Block Diagram of Port B
  515
Appendix D Port States in the Different Processing States

516
Appendix E List of Product Codes

517
Appendix F Package Dimensions

518

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