Register Descriptions; A/D Data Registers A To D (Addra To Addrd) - Hitachi F-ZTAT H8/3039 Series Hardware Manual

13.2 Register Descriptions

13.2.1 A/D Data Registers A to D (ADDRA to ADDRD)

Bit 15
ADDRn AD9
Initial value 0
Read/Write R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that always read 0. Table 13-3 indicates the pairings of analog input
channels and A/D data registers.
The CPU can always read the A/D data registers. The upper byte can be read directly, but the
lower byte is read through a temporary register (TEMP). For details see section 13.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 13-3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
AN0
AN1
AN2
AN3
14 13 12 11
AD8 AD6
AD7 AD5
0 0 0 0
R R R R
A/D conversion data
10-bit data giving an
A/D conversion result
Group 1
AN4
AN5
AN6
AN7
10 9 8 7
AD4 AD2
AD3 AD1
0 0 0 0
R R R R
6 5 4 3
AD0
— — —
0 0 0 0
R R R R
Reserved bits
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
2 1 0
—
— —
0 0 0
R R R
415