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6.2.4 Address Control Register (ADRCR)
ADRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21.
Bit
Initial value
Mode
1 and 5 to 7
Read/Write
Initial value
Mode
3
Read/Write
ADRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Address 23 Enable (A
0 in this bit enables A
modified and PA4 has its ordinary input/output functions
Bit 7
A
E
Description
23
0
PA
1
PA
Bit 6—Address 22 Enable (A
0 in this bit enables A
modified and PA
has its ordinary input/output functions.
5
Bit 6
A
E
Description
22
0
PA
1
PA
7
6
A
E
A
23
22
1
1
—
—
1
1
R/W
R/W
Address 23 to 21 enable
These bits enable PA
PA
to be used for A
4
A
address output
21
E): Enables PA4 to be used as the A
23
address output from PA4. In modes other than 3 this bit cannot be
23
is the A
address output pin
4
23
is the PA
/TP
/TIOCA
4
4
4
E): Enables PA
22
address output from PA
22
is the A
address output pin
5
22
is the PA
/TP
/TIOCB
5
5
5
5
4
E
A
E
—
21
1
1
—
—
1
1
R/W
—
to
6
to
23
input/output pin
1
to be used as the A
5
. In modes other than 3 this bit cannot be
5
input/output pin
1
3
2
1
—
—
—
1
1
1
—
—
—
1
1
1
—
—
—
Reserved bits
address output pin. Writing
23
(Initial value)
address output pin. Writing
22
(Initial value)
0
—
0
R/W
0
R/W
115
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