Hitachi F-ZTAT H8/3039 Series Hardware Manual page 206

Table 8-3 ITU Registers (cont)
Channel Address*
2 H'FF78
H'FF79
H'FF7A
H'FF7B
H'FF7C
H'FF7D
H'FF7E
H'FF7F
H'FF80
H'FF81
3 H'FF82
H'FF83
H'FF84
H'FF85
H'FF86
H'FF87
H'FF88
H'FF89
H'FF8A
H'FF8B
H'FF8C
H'FF8D
H'FF8E
H'FF8F
Notes: 1. The lower 16 bits of the address are indicated.
2. Only 0 can be written, to clear flags.
196
1
Name
Timer control register 2
Timer I/O control register 2
Timer interrupt enable register 2
Timer status register 2
Timer counter 2 (high)
Timer counter 2 (low)
General register A2 (high)
General register A2 (low)
General register B2 (high)
General register B2 (low)
Timer control register 3
Timer I/O control register 3
Timer interrupt enable register 3
Timer status register 3
Timer counter 3 (high)
Timer counter 3 (low)
General register A3 (high)
General register A3 (low)
General register B3 (high)
General register B3 (low)
Buffer register A3 (high)
Buffer register A3 (low)
Buffer register B3 (high)
Buffer register B3 (low)
Abbre-
viation R/W
TCR2 R/W
TIOR2 R/W
TIER2 R/W
2
TSR2 R/(W)*
TCNT2H R/W
TCNT2L R/W
GRA2H R/W
GRA2L R/W
GRB2H R/W
GRB2L R/W
TCR3 R/W
TIOR3 R/W
TIER3 R/W
2
TSR3 R/(W)*
TCNT3H R/W
TCNT3L R/W
GRA3H R/W
GRA3L R/W
GRB3H R/W
GRB3L R/W
BRA3H R/W
BRA3L R/W
BRB3H R/W
BRB3L R/W
Initial
Value
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'80
H'88
H'F8
H'F8
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF
H'FF