Table A-3 Number of States per Cycle
Cycle
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Legend
m: Number of wait states inserted in external device access
580
On-Chip Sup-
porting Module
On-Chip
8-Bit
Memory
Bus
S
2
6
I
S
J
S
K
S
3
L
S
6
M
S
1
N
Access Conditions
8-Bit Bus
16-Bit
2-State
3-State
Bus
Access
Access
3
4
6 + 2m 2
2
3 + m
4
6 + 2m
External Device
16-Bit Bus
2-State
3-State
Access
Access
3 + m