Hitachi F-ZTAT H8/3039 Series Hardware Manual page 477

Figure 15-13 shows the flash memory state transition diagram.
Notes: 1. This is the state in which the P or E bit in FLMCR is set to 1. In this state, NMI input is
disabled. For more information, see section 15.6.4, NMI Input Disable Conditions.
2. For a detailed description of the FLER bits setting conditions, see section 15.3.4, Flash
Memory Status Register (FLMSR).
3. Data can be written to FLMCR and EBR. However, when transition to the software
standby mode was made in the error protection state, the registers are initialized.
Memory read verify mode
RD VF PR ER FLER=0
P=1 or E=1
P=0 and E=0
Program mode
Erase mode
RD VF PR ER FLER=0
Error occurrence
Error protection mode
RD VF PR ER FLER=1
RD : Memory read enable
VF : Verify-read enable
PR : Programming enable
ER : Erasing enable
(When High level apply to FWE pin in modes 5 and 7 (on-chip ROM enabled))
The error protection function is disabled for errors other than the FLER bit set conditions. If
considerable time elapses up to transit to this protection state, the flash memory may already be
damaged. As a result, this function cannot completely protect the flash memory against damage.
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Reset or hardware standby mode
standby mode
Software standby
mode release
RD
VF
PR
ER
INIT
Figure 15-13 Flash Memory State Transitions
Software
(software standby mode)
RD VF PR ER INIT FLER=1
: Memory read disabled
: Verify-read disabled
: Programming disabled
: Erasing disabled
: Registers (FLMCR, EBR) initialize state
Reset or standby mode
(hardware protection)
RD VF PR ER INIT FLER=0
Reset or hardware
standby mode
Error protection mode