Clearing Of Status Flags - Hitachi F-ZTAT H8/3039 Series Hardware Manual

Single-chip microcomputer
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ø
TCNT
Overflow
signal
OVF
OVI

8.5.2 Clearing of Status Flags

If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is
cleared. Figure 8-60 shows the timing.
ø
Address
IMF, OVF
268
H'FFFF
Figure 8-59 Timing of Setting of OVF
Figure 8-60 Timing of Clearing of Status Flags
H'0000
TSR write cycle
T
T
1
2
TSR address
T
3

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F-ztat h8/3039F-ztat h8/3038F-ztat h8/3037F-ztat h8/3036

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