Hitachi F-ZTAT H8/3039 Series Hardware Manual page 315

Example of Normal TPC Output (Example of Five-Phase Pulse Output): Figure 9-5 shows an
example in which the TPC is used for cyclic five-phase pulse output.
TCNT value
TCNT
GRA
H'0000
NDRA 80 C0
PADR 00 80
TP
7
TP
6
TP
5
TP
4
TP
3
• The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare
register and the counter will be cleared by compare match A. The trigger period is set in GRA.
The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt.
• H'F8 is written in PADDR and NDERA, and bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 are set in
TPCR to select compare match in the ITU channel set up in step 1 as the output trigger.
Output data H'80 is written in NDRA.
• The timer counter in this ITU channel is started. When compare match A occurs, the NDRA contents
are transferred to PADR and output. The compare match/input capture A (IMFA) interrupt service routine
writes the next output data (H'C0) in NDRA.
• Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing
H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive IMFA interrupts.
Figure 9-5 Normal TPC Output Example (Five-Phase Pulse Output)
Compare match
40 60 20
C0 40 60 20
30 10 18 08
30 10 18
88 80 C0
08 88 80 C0
Time
40
305