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8.1.3
Input/Output Pins.................................................................................................. 193
8.1.4
Register Configuration ......................................................................................... 195
8.2
Register Descriptions......................................................................................................... 198
8.2.1
Timer Start Register (TSTR)................................................................................ 198
8.2.2
Timer Synchro Register (TSNC).......................................................................... 199
8.2.3
Timer Mode Register (TMDR) ............................................................................ 201
8.2.4
Timer Function Control Register (TFCR)............................................................ 204
8.2.5
Timer Output Master Enable Register (TOER).................................................... 206
8.2.6
Timer Output Control Register (TOCR) .............................................................. 209
8.2.7
Timer Counters (TCNT)....................................................................................... 210
8.2.8
General Registers (GRA, GRB) ........................................................................... 211
8.2.9
Buffer Registers (BRA, BRB).............................................................................. 212
8.2.10 Timer Control Registers (TCR)............................................................................ 213
8.2.11 Timer I/O Control Register (TIOR) ..................................................................... 216
8.2.12 Timer Status Register (TSR) ................................................................................ 218
8.2.13 Timer Interrupt Enable Register (TIER) .............................................................. 220
8.3
CPU Interface .................................................................................................................... 222
8.3.1
16-Bit Accessible Registers.................................................................................. 222
8.3.2
8-Bit Accessible Registers ................................................................................... 224
8.4
Operation ........................................................................................................................... 225
8.4.1
Overview .............................................................................................................. 225
8.4.2
Basic Functions .................................................................................................... 226
8.4.3
Synchronization.................................................................................................... 236
8.4.4
PWM Mode .......................................................................................................... 238
8.4.5
Reset-Synchronized PWM Mode ......................................................................... 242
8.4.6
Complementary PWM Mode ............................................................................... 245
8.4.7
Phase Counting Mode .......................................................................................... 255
8.4.8
Buffering .............................................................................................................. 257
8.4.9
ITU Output Timing .............................................................................................. 264
8.5
Interrupts............................................................................................................................ 266
8.5.1
Setting of Status Flags.......................................................................................... 266
8.5.2
Clearing of Status Flags........................................................................................ 268
8.5.3
Interrupt Sources .................................................................................................. 269
8.6
Usage Notes ....................................................................................................................... 270
Section 9
9.1
Overview............................................................................................................................ 285
9.1.1
Features ................................................................................................................ 285
9.1.2
Block Diagram...................................................................................................... 286
9.1.3
TPC Pins............................................................................................................... 287
9.1.4
Registers ............................................................................................................... 288
9.2
Register Descriptions......................................................................................................... 289
9.2.1
Port A Data Direction Register (PADDR) ........................................................... 289
.............................................. 285
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