Internal Interrupts; Interrupt Vector Table - Hitachi F-ZTAT H8/3039 Series Hardware Manual

Figure 5-3 shows the timing of the setting of the interrupt flags (IRQnF).
ø
IRQn
input pin
IRQnF
Note: n = 5, 4, 1 and 0
Interrupts IRQ , IRQ
5
detected regardless of whether the corresponding pin is set for input or output. When using a pin
for external interrupt input, clear its DDR bit to 0 and do not use the pin for SCI input or output.

5.3.2 Internal Interrupts

Twenty-five internal interrupts are requested from the on-chip supporting modules.
• Each on-chip supporting module has status flags for indicating interrupt status, and enable bits
for enabling or disabling interrupts.
• Interrupt priority levels can be assigned in IPRA and IPRB.

5.3.3 Interrupt Vector Table

Table 5-3 lists the interrupt sources, their vector addresses, and their default priority order. In the
default priority order, smaller vector numbers have higher priority. The priority of interrupts other
than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order
shown in table 5-3.
Figure 5-3 Timing of Setting of IRQnF
, IRQ , IRQ have vector numbers 17, 16, 13, 12. These interrupts are
4 1 0
95