Appendix E Timing Of Transition To And Recovery From Hardware Standby Mode - Hitachi F-ZTAT H8/3039 Series Hardware Manual

Appendix E Timing of Transition to and Recovery from
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10
system clock cycles before the STBY signal goes low, as shown below. RES must remain low
until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
RES
(2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, RES does not have to be
driven low as in (1).
Timing of Recovery from Hardware Standby Mode: Drive the RES signal low approximately
100 ns before STBY goes high.
STBY
RES
Hardware Standby Mode
≥ 10t
t
1 cyc
t ≥ 100 ns
≥ 0 ns
t
2
t
OSC
679