Hitachi F-ZTAT H8/3039 Series Hardware Manual page 573

Table A-1 Instruction Set (cont)
Mnemonic
DIVXU. W Rs, ERd
DIVXS. B Rs, Rd
DIVXS. W Rs, ERd
CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W #xx:16, Rd
CMP.W Rs, Rd
CMP.L #xx:32, ERd
CMP.L ERs, ERd
NEG.B Rd
NEG.W Rd
NEG.L ERd
EXTU.W Rd
EXTU.L ERd
EXTS.W Rd
EXTS.L ERd
Operation
W ERd32 ÷ Rs16 →ERd32
(Ed: remainder,
Rd: quotient)
(unsigned division)
Rd16 ÷ Rs8 → Rd16
B
(RdH: remainder,
RdL: quotient)
(signed division)
W ERd32 ÷ Rs16 → ERd32
(Ed: remainder,
Rd: quotient)
(signed division)
B Rd8–#xx:8
B Rd8–Rs8
W Rd16–#xx:16
W Rd16–Rs16
L ERd32–#xx:32
L ERd32–ERs32
0–Rd8 → Rd8
B
W 0–Rd16 → Rd16
0–ERd32 → ERd32
L
W 0 → (<bits 15 to 8>
of Rd16)
0 → (<bits 31 to 16>
L
of Rd32)
W (<bit 7> of Rd16) →
(<bits 15 to 8> of Rd16)
(<bit 15> of Rd32) →
L
(<bits 31 to 16> of
ERd32)
Addressing Mode and
Instruction Length (bytes)
2
4
4
2
2
4
2
6
2
2
2
2
2
2
2
2
No. of
States
Condition Code
I H N Z V C
— — (6) (7) — —
— — (8) (7) — —
— — (8) (7) — —
—
—
— (1)
— (1)
— (2)
— (2)
—
—
—
— — 0 0 —
— — 0 0 —
— — 0 —
— — 0 —
*1
22
16
24
2
2
4
2
4
2
2
2
2
2
2
2
2
567