Hitachi Relion 650 Series Technical Manual page 264

Section 12
Monitoring
Similarly, for phase L2 and phase L3, the alarm status are set. The information for all the ten inputs in
three-phases are divided into two 32 bit outputs. Here, output 1 is designated as ALS1T5 and output
2 is designated as ALS6T10. The last two bits in both outputs are unused.
Calculating alarm status bits for analog input signals
Example for alarm status calculation for analog input signals 1-9:
Consider for any input x for phase n, if Warning (Low Warning/High Warning) information is set, then:
[ 6·(x-1) + 2·(n-1) ]
If Alarm (Low Alarm/High Alarm) information needs to be set, then:
[ 6·(x-1) + 2·(n-1) +1 ]
The Alarm and Warning information for selected examples is shown in
Table 252: Alarm and Warning information for analog input signals
Input
1
1
1
2
2
2
3
3
3
4
4
4
5
5
5
ALS1T5 becomes 00110101011000110100101001011001 in binary, that is 895699545 in decimal.
During the bit packing, the 30
Similar procedure is carried out for ALS6T10
Calculating alarm status bits for binary input signals
Example for alarm status calculation for binary input 10:
258
th
bit position in alarm status output goes high.
th
bit position in alarm status output goes high.
phase Assumed alarm range
L1 High Warning
L2 Low Alarm
L3 Low Warning
L1 Low Warning
L2 High Alarm
L3 Low Alarm
L1 Normal
L2 High Warning
L3 Alarm Input is high
L1 Normal
L2 Low Alarm
L3 Low Warning
L1 Low Warning
L2 High Warning
L3 Alarm Input is high
th
and 31
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st
bits are not used (set as zero).
1MRK 511 557-UEN Rev. A
GUID-BC10CFB6-4B39-4218-B134-0E5A55D1DD47 v2
Table 252.
Bit position
6·(1-1)+2·(1-1) =0
th
0 bit set high
6·(1-1)+2·(2-1)+1 =3
rd
3 bit set high
6·(1-1)+2·(3-1) =4
th
4 bit set high
6·(2-1)+2·(1-1) =6
th
6 bit set high
6·(2-1)+2·(2-1)+1 =9
th
9 bit set high
6·(2-1)+2·(3-1)+1 =11
th
11 bit set high
th th
both 12 and 13 bit set low
6·(3-1)+2·(2-1) =14
th
14 bit set high
th th
both 16 and 17 bit set high
th th
both 18 and 19 bit set low
6·(4-1)+2·(2-1)+1 =21
st
21 bit set high
6·(4-1)+2·(3-1) =22
nd
22 bit set high
6·(5-1)+2·(1-1) =24
th
24 bit set high
6·(5-1)+2·(2-1) =26
th
26 bit set high
th th
both 28 and 29 bit set high
GUID-B16C1FEF-36F9-4ECB-9E5A-4331029DB904 v2
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