Toshiba TLCS-900/H1 Series Manual page 525

(11) UART/serial channel (1/2)
Symbol Name Address
Serial
1200H
channel 0
SC0BUF (Prohibit
buffer
RMW)
register
Serial
channel 0
SC0CR 1201H
control
register
Serial
channel 0
SC0MOD0 1202H
mode 0
register
Serial
channel 0
BR0CR baud rate 1203H
control
register
Serial
channel 0
BR0ADD 1204H
K setting
register
Serial
channel 0
SC0MOD1 1205H
mode 1
register
IrDA
SIRCR control 1207H
register
7 6 5
RB7 RB6 RB5
TB7 TB6 TB5
RB8 EVEN PE
R R/W
Undefined 0 0
Receive Parity Parity
data bit8 0: Odd 0: Disable
1: Even 1: Enable
TB8 CTSE RXE
0 0 0
Trans- 0: CTS 0: Receive
mission disable disable
data bit8 1: CTS 1: Receive
enable
enable
−
BR0ADDE BR0CK1
0 0 0
00: φT0
Always (16-K)/16
01: φT2
write "0" divided
10: φT8
0: Disable
11: φT32
1: Enable
I2S0 FDPX0
R/W R/W
0 0
IDLE2 Duplex
0: Stop
0: Half duplex
1: Operate
1: Full duplex
PLSEL RXSEL TXEN
0 0 0
Select Receive Transmit
transmit data 0: Disable
pulse 1: Enable
0: "H" pulse
width
1: "L" pulse
0: 3/16
1: 1/16
92CH21-523
4 3
RB4 RB3
TB4 TB3
R (Receiving)/W (Transmission)
Undefined
OERR PERR
R (Clear 0 after reading)
0 0
1: Error
Overrun Parity Framing
WU SM1
R/W
0 0
Wake-up 00: I/O Interface mode
0: Disable 01: 7-bit UART mode
1: Enable 10: 8-bit UART mode
11: 9-bit UART mode
BR0CK0 BR0S3
R/W
0 0
Divided frequency setting
BR0K3
0
Sets frequency divisor "K"
(divided by N + (16 − K)/16).
RXEN SIRWD3
R/W
0 0
Receive
Select receive pulse width
0: Disable
Set effective pulse width for equal or more
1: Enable
than 2x × (value + 1) + 100ns
Can be set: 1 to 14
Can not be set: 0,15
TMP92CH21
2 1 0
RB2 RB1 RB0
TB2 TB1 TB0
FERR SCLKS IOC
R/W
0 0 0
0: SCLK0 ↑
0: Baud
1: SCLK0 ↓
rate
generator
1: SCLK0
pin input
SM0 SC1 SC0
0 0 0
00: TA0TRG
01: Baud rate
generator
10: Internal clock f
11: External clock
(SCLK0 input)
BR0S2 BR0S1 BR0S0
0 0 0
BR0K2 BR0K1 BR0K0
R/W
0 0 0
SIRWD2 SIRWD1 SIRWD0
0 0 0
2009-06-19
IO