Toshiba TLCS-900/H1 Series Manual page 516

(6) LCD controller (1/6)
Symbol Name Address
LCD
mode 0 0280H
LCDMODE0
register
LCD
mode 1 0281H
LCDMODE1
register
LCD frame
LCDFFP frequency 0282H
register
LCD
LCDDVM divide FRM 0283H
register
LCD size
LCDSIZE 0284H
register
LCD
control 0 0285H
LCDCTL0
register
LCD
control 1 0286H
LCDCTL1
register
7 6 5
RAMTYPE1 RAMTYPE0 SCPW1
0 0 1
Display RAM LD bus transmission
speed
00: Internal SRAM 00: Reserved
01: 2 × f
01: External SRAM
10: SDRAM
10: 4 × f
11: Reserved
11: 8 × f
LLPMODE
0
LLP mode
0: mode1
1: mode2
FP7 FP6 FP5
0
0 0
FMN7 FMN6 FMN5
0 0 0
COM3 COM2 COM1
0 0 0
Common setting
0000: Reserved 0101: 200
0001: 64 0110: 240
0010: 120 0111: 320
0011: 128 1000: 480
0100: 160 Others: Reserved
ALL0 FRMON
0 0
Column FR divide
Data setting
setting 0: Disable
0: Normal 1: Enable
1: All
display
data "0"
LCP0P LCP1P LBCDP
R/W R/W R/W
1 0 0
LCP0 LCP1 LBCD
phase phase phase
0: Rising 0: Rising 0: Low
1: Falling 1: Falling 1: High
92CH21-514
4 3
SCPW0 MODE3
R/W
0 0
Mode setting
0000: Built-in RAM type
0001: SR 1bpp (mono)
0010: SR 2bpp (4gray)
SYS
0011: SR 3bpp (8gray)
SYS
0100: SR 4bpp (16gray)
SYS
LDINV AUTOINV
R/W
0 0
LD bus Auto LD Select
inversion bus interrupt
0: Normal inversion 0: LP
1: Inversion 0: Disable 1: BCD
1: Enable
(Valid in
TFT mode)
FP4 FP3
R/W
0 0
Setting bit7 to bit0 f
FP
FMN4 FMN3
R/W
0 0
Setting DVM bit7 to bit0
COM0 SEG3
R/W
0 0
Segment setting
0000: Reserved 0101: 320
0001: 64
0010: 128
0011: 160
0100: 256 1001: 960 Others: Reserved
−
FP9
R/W
0 0
Always f Built-in
FP setting
write "0" 9 RAM LCDD
bit
setting
0:
Sequential
access
1: Random
TMP92CH21
2 1 0
MODE2 MODE1 MODE0
0 0 0
0101: STN 8bpp (256)
0110: STN 12bpp (4096)
0111: Reserved
1000: TFT 8bpp (256)
1001: TFT 12bpp (4096)
Others: Reserved
INTMODE LDO1 LDO0
0 0 0
LD bus width control
00: 4bit width A_type
01: 4bit width B_type
10: 8bit width A_type
11: 8bit width B_type
Others: Reserved
FP2 FP1 FP0
0 0 0
FMN2 FMN1 FMN0
0 0 0
SEG2 SEG1 SEG0
0 0 0
0110: 480
0111: 640
1000: 768
MMULCD FP8 START
0 0 0
f LCDC start
FP setting
0: STOP
bit 8
1: START
access
LBCDW1 LBCDW0
R/W R/W
0 0
LBCD width control
00: LCP1_1CLK
01: LCP1_2CLK
10: LCP1_3CLK
11: Reserved
2009-06-19