Toshiba TLCS-900/H1 Series Manual page 201

bit Symbol
USBINTFR4
(07F3H)
Read/Write
Reset State
Function
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
7 6
INT_SETUP INT_EP0 INT_STAS
R/W R/W
0 0
When read 0: Not generate interrupt
1: Generate interrupt
• INT_SETUP (Bit7)
This is the flag register for INT_SETUP (setup - interrupt).
This is set to "1" when the UDC receives a request that S/W (software)
control is needed from USB host.
Using S/W (INT_SETUP routine), first read 8-byte device requests from the
UDC and execute operation according to each request.
•
INT_EP0 (Bit6)
This is the flag register for INT_EP0 (received data of the data phase for
Control transfer type - interrupt).
This is set to "1" when the UDC receives data of the data phase for Control
transfer type. If this interrupt occurs during Control write transfer, data
reading from FIFO is needed. If this interrupt occurs during Control read
transfer, transmission data writing to FIFO is needed.
In some cases, the host may not assert "ACK" of the last packet in the data
stage. In this case, this interrupt cannot be generated. Therefore, ignore this
interrupt if it occurs after the last packet data has been written in the data
stage because the transmission data number is specified by the host, or it
depends on the capacity of the device.
• INT_STAS (Bit5)
This is the flag register for INT_STAS (status stage end - interrupt).
This is set to "1" when the status stage ends.
If this interrupt is generated, it means that request ended normally.
If this interrupt is not generated and INT_SETUP is generated,
EP0_STATUS <STAGE_ERR> is set to "1", and it means that request did not
end normally.
5 4 3
INT_STASN INT_EP1N
R/W R/W R/W
0 0 0
When write
92CH21-199
2 1
INT_EP2N INT_EP3N
R/W R/W
0 0
0: Clear flag
1: −
TMP92CH21
0
EP2_Empty_B
R/W
0
2009-06-19