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Toshiba TLCS-900/H1 Series Manual page 522

Original cmos 32-bit microcontroller
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(7) Touch screen I/F
Symbol
Name
Address
Touch
screen I/F
TSICR0
01F0H
control
register 0
Touch
screen I/F
TSICR1
01F1H
control
register 1
(8) SDRAM controller
Symbol
Name
Address
SDRAM
access
SDACR1
0250H
control
register 1
SDRAM
access
SDACR2
0251H
control
register 2
SDRAM
refresh
SDRCR
0252H
control
register
SDRAM
SDCMM
command
0253H
register
7
6
5
TSI7
PTST
R/W
R
0
0
0: Disable
Detection
1: Enable
condition
0: no
touch
1: touch
DBC7
DB1024
DB256
R/W
R/W
R/W
0
0
0
0: Disable
1024
256
De-bounce time is set by "(N × 64 − 16)/f
1: Enable
"N" is sum of number which is set to "1" in bit6 to bit0.
7
6
5
SMRD
0
0
0
Always
Always
Mode
write "0"
write "0"
register
set delay
time
0:1 clock
1:2 clocks
92CH21-520
4
3
2
TWIEN
PYEN
PXEN
R/W
R/W
R/W
0
0
0
INT4
SPY
SPX
interrupt
0 : OFF
0 : OFF
control
1 : ON
1 : ON
0: Disable
1: Enable
DB64
DB8
DB4
R/W
R/W
R/W
0
0
0
64
8
4
4
3
2
SWRC
SBST
SBL1
R/W
0
0
1
Write
Burst stop
Select read burst
recovery
command
length
time
00: Reserved
0: recharge
01: Full page read,
0:1 clock
all
Burst write
1:2 clocks
1:Burst
10: 1 word read,
stop
Single write
11: Full page read
Single write
SBS
SDRS1
SDRS0
0
0
0
Number
Selecting ROW
of banks
address size
SRS2
SRS1
0
0
Refresh interval
000: 47 states
001: 78 states
010: 97 states
011: 124 states
SCMM2
0
TMP92CH21
1
0
MYEN
MXEN
R/W
R/W
0
0
SMY
SMX
0 : OFF
0 : OFF
1 : ON
1 : ON
DB2
DB1
R/W
R/W
0
0
2
1
" − formula.
SYS
1
0
SBL0
SMAC
0
0
SDRAM
controller
0: Disable
1: Enable
SMUXW1 SMUXW0
R/W
0
0
Selecting address
Multiplex type
SRS0
SRC
R/W
0
0
Auto
100: 156 states
refresh
101: 295 states
0: Disable
110: 249 states
1: Enable
111: 312 states
SCMM1
SCMM0
R/W
0
0
Issuing command
2009-06-19

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