Toshiba TLCS-900/H1 Series Manual page 342

3.14.3 Shift Register Type LCD Driver Control Mode (SR mode and STN color)
3.14.3.1 Description of Operation
Set the mode of operation, start address of source data save memory, grayscale level
and LCD size to control registers before setting start register.
After setting start register, the LCDC outputs a bus release request to the CPU and
reads data from source memory. After data reading from source data is completed, the
LCDC cancels the bus release request and the CPU will restart. The LCDC then
transmits LCD size data to the external LCD driver through the LD bus (special data
bus only for LCD driver). At this time, the control signals (LCP0 etc.) connected to the
LCD driver output the specified waveform which is synchronized with the data
transmission.
The LCD controller generates control signals (LFR, LBCD, LLP etc.) from base clock
LCDSCC. LCDSCC is the base clock for the LCD controller, which is generated by
system clock f
This LSI has a special clock generator for the LCDC. Details of LCD frame refresh
rate can be set using this special generator. This generator is made from an 8-bit
counter and 1/16 speed clock from the system clock.
Note 1: During data read from source memory (during DMA operation), the CPU is
stopped by the internal BUSREQ signal. When using SR mode LCDC,
programmers must monitor CPU performance.
Note 2: This LSI has a 16-Kbyte SRAM, this internal RAM is available for use as display
RAM. Internal RAM access is very fast (32-bit bus width, 1 SYSCLK read/write), it
is possible to reduce CPU load to a minimum, enabling LCDC DMA.
This LCDC supports monochrome, 2 bpp (4 grayscales), 3 bpp (8 grayscales), 4 bpp
(16 grayscales), 8 bpp (256 colors) and 12 bpp (4096 colors). Display RAM is supported
by external SDRAM, SRAM and internal RAM (16 Kbytes).
It is automatically set to suitable condition data correction against interference
between pixels in panels. Special adjustment is not required.
In passive matrix STN mode, 8 bpp (256 colors) is supported out of a palette of 4096
colors. Support is also given for 4096 colors out of a pallet of 4096 colors.
Data output width is selectable between 4 bits or 8 bits, and data output sequence
selectable between 2 modes.
SR type LCD control setting is described below.
SYS
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92CH21-340
TMP92CH21
2009-06-19