Toshiba TLCS-900/H1 Series Manual
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Toshiba TLCS-900/H1 Series Manual

Toshiba TLCS-900/H1 Series Manual

Original cmos 32-bit microcontroller
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TOSHIBA Original CMOS 32-Bit Microcontroller
TLCS-900/H1 Series
TMP92CH21FG
Semiconductor Company

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  • Page 1 TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CH21FG Semiconductor Company...
  • Page 2 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Points of Note and Restrictions”.
  • Page 3 TMP92CH21 CMOS 32-bit Microcontroller TMP92CH21FG/JTMP92CH21 Outline and Device Characteristics The TMP92CH21 is a high-speed advanced 32-bit Microcontroller developed for controlling equipment which processes mass data. The TMP92CH21 has a high-performance CPU (900/H1 CPU) and various built-in I/Os. The TMP92CH21FG is housed in a 144-pin flat package. The JTMP92CH21 is a chip form product.

  • Page 4: Internal Memory

    TMP92CH21 (3) Internal memory • Internal RAM: 16 Kbytes (can be used for program, data and display memory) • Internal ROM: 8 Kbytes (used as boot program) Possible downloading of user program through either USB, UART or NAND flash. (4) External memory expansion •...
  • Page 5 VCC = 3.0 V to 3.6 V (fc max = 40 MHz) • VCC = 2.7 V to 3.6 V (fc max = 27 MHz) (26) Package: • 144-pin QFP (P-LQFP144 -1616-0.40C) • 144-pin chip form is also available. For details, contact your local Toshiba sales representative. 2006-09-15 92CH21-3...
  • Page 6 TMP92CH21 PG0 to PG1 DVCC [4] (AN0 to AN1) DVSS [3] 900/H1 CPU AN2/MX (PG2) 10-bit AN3/MY/ (PG3) 4-channel ADTRG H-OSC AD converter AVCC, AVSS VREFH, VREFL Clock gear TEST Touch (PX, INT4) P96 screen (PY, INT5) P97 L-OSC I/F (TSI) RESET (TXD0, TXD1) PF0 Serial I/O...

  • Page 7: Pin Assignment

    TMP92CH21 Pin Assignment and Functions The assignment of input/output pins for the TMP92CH21FG, their names and functions are as follows: Pin Assignment VREFL P67, A23 VREFH P66, A22 PG0, AN0 P65, A21 PG1, AN1 P64, A20 PG2, AN2, MX DVCC3 PG3, AN3, , MY ADTRG...

  • Page 8: Pad Assignment

    TMP92CH21 PAD Assignment (Chip size 5.98 mm × 6.42 mm) Table 2.2.1 Pad Assignment Diagram (144-pin chip) Unit: μm Name Name Name Point Point Point Point Point Point −2852 −488 −3072 2671 DVSS2 2848 VREFL −2852 −338 −3072 2546 DVCC2 2848 VREFH −2852...

  • Page 9: Pin Names And Functions

    TMP92CH21 Pin Names and Functions The following table shows the names and functions of the input/output pins Table 2.3.1 Pin Names and Functions (1/5) Number of Pin Name Function Pins D0 to D7 Data: Data bus 0 to 7 P10 to P17 Port 1: I/O port input or output specifiable in units of bits D8 to D15 Data: Data bus 8 to 15...
  • Page 10 TMP92CH21 Table 2.3.2 Pin Names and Functions (2/5) Number of Pin Name Function Pins Output Port80: Output port Output Chip select 0: Outputs “low” when address is within specified address area Output Port81: Output port Output Chip select 1: Outputs “low” when address is within specified address area Output Chip select for SDRAM: Outputs “0”...
  • Page 11 TMP92CH21 Table 2.3.3 Pin Names and Functions (3/5) Number of Pin Name Function Pins Port C0: I/O port (Schmitt-input) INT0 Input Interrupt request pin 0: Interrupt request pin with programmable level/rising/falling edge TA1OUT Output 8-bit timer 1 output: Timer 1 output Port C1: I/O port (Schmitt-input) INT1 Input...
  • Page 12 TMP92CH21 Table 2.3.4 Pin Names and Functions (4/5) Number of Pin Name Function Pins Output Port J0: Output port Output Row address strobe for SDRAM SDRAS Output Data enable for SRAM on pins D0 to D7 SRLLB Output Port J1: Output port Output Column address strobe for SDRAM SDCAS...
  • Page 13 TMP92CH21 Table 2.3.5 Pin Names and Functions (5/5) Number of Pin Name Function Pins USB-data connecting pin D+, D− Connect pull-up resistor to both pins to avoid through current when USB is not in use. Operation mode: Fix to AM1 = “0”, AM0 = “1” for 16-bit external bus starting AM0, AM1 Input Fix to AM1 = “1”, AM0 = “0”...

  • Page 14: Operation

    TMP92CH21 Operation This section describes the basic components, functions and operation of the TMP92CH21. The TMP92CH21 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process instructions more quickly.
  • Page 15 TMP92CH21 3.1.2 Reset Operation When resetting the TMP92CH21, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the input low for at least 20 system clocks (16 µs at fc = 40 MHz). RESET At reset, since the clock doubler (PLL) is bypassed and the clock-gear is set to 1/16, the system clock operates at 1.25 MHz (fc = 40 MHz).
  • Page 16 TMP92CH21 Write Read Figure 3.1.2 TMP92CH21 Reset Timing Chart 2006-09-15 92CH21-14...

  • Page 17: Operation Mode

    TMP92CH21 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup Input Pin Operation Mode RESET 16-bit external bus starting (MULTI 16 mode) 32-bit external bus starting (MULTI 32 mode) Boot (32-bit internal MROM) starting...

  • Page 18: Memory Map

    TMP92CH21 Memory Map Figure 3.2.1 is a memory map of the TMP92CH21. 000000H Internal I/O Direct area (n) (8 Kbytes) 000100H 001D00H 002000H 64-Kbyte area Internal RAM (nn) (16 Kbytes) 006000H 010000H 3FE000H Boot (Internal MROM) (Note 1) (8 Kbytes) 400000H External memory F00000H...
  • Page 19 TMP92CH21 3.21.2 Hardware Specification for Internal Boot ROM (1) Memory map Figure 3.21.1 shows a memory map of BOOT mode. An 8-Kbyte ROM is built-in and it is mapped to address 3FE000H to 3FFFFFH. In MULTI mode, the boot ROM is not mapped and its area is mapped as an external area.
  • Page 20 TMP92CH21 3.21.3 Outline of Boot Operation There are 3 downloading methods: NAND flash, UART and USB. After reset, a boot program in the boot ROM operates as shown in the Figure 3.21.2 flow chart. Internal RAM use is the same regardless of downloading method, and is shown in Figure 3.21.3.
  • Page 21 TMP92CH21 002000H Work area for boot program (4 Kbytes) 003000H Download area for user program (10 Kbytes) 005800H Stack area for boot program (2 Kbytes) Figure 3.21.3 Internal RAM Use 2006-09-15 92CH21-438...

  • Page 22: Port Setting

    TMP92CH21 (1) Port setting The boot program port settings are shown in Table 3.21.3, and Table 3.21.4 shows PCB design. These port settings must be carefully noted when designing an application system. The remaining ports are not set, so they maintain their status after reset. Table 3.21.3 Port Setting Port Setting by Boot Program Port...

  • Page 23: Boot Method

    TMP92CH21 Table 3.21.4 How to Design PCB Boot Method Port Function UART NAND flash Not affected by UART boot. Not affected by USB boot. NAND Output Connect to NAND flash and NDRE If the NAND flash is not used in flash pull-up by 100 kΩ...
  • Page 24 TMP92CH21 (2) I/O registers setting by boot program Table 3.21.5 shows I/O register setting by boot program. Take particular note of these set values when using an application system program which continues to run without asserting a reset after a boot sequence is executed . Also take note of the status of the CPU registers and internal RAM following execution of a boot sequence.
  • Page 25 TMP92CH21 3.21.4 Download from NAND flash (1) Connection example Figure 3.21.4 shows an example of NAND flash. (A 16-bit SDRAM is used as program memory). 100 kΩ 2 kΩ 100 kΩ P84, PJ6, NDCLE PJ5, NDALE P71, NDRE TMP92CH21 P72, NDWE P75, NDR/ B PF7, SDCLK...

  • Page 26: Data Format

    TMP92CH21 (3) Data format The download data consists of the boot identification code (4 bytes), user program size (2 bytes) and user program (max 10 Kbytes). These should be assigned (programmed) to NAND flash as shown in Figure 3.21.5. Also program the ECC code in the redundant area of the NAND flash, the block status area and thedata status area .
  • Page 27 TMP92CH21 User program (max 10 Kbytes) This refers to a user program that is loaded to internal RAM. When creating a user program, note the following points. • Set start address to 3000H Beforehand, program (write) the user program to NAND flash in binary format.
  • Page 28 TMP92CH21 (4) Error check item The items checked by the boot program are given below. If an error occurs in any check, the boot program will cancel downloading from NAND flash and skip to the next operation (recognizing UART or USB). Supported NAND flash The boot program reads a device code from NAND flash and checks whether it is supported or not.
  • Page 29 TMP92CH21 For reference, details of calculation flow are given below. Make XOR data by calculating exclusive OR after both ECC code from NDFC and NAND flash are placed to 4-byte data as below. Lower 2 bytes: Line parity Upper 2 bytes: Column parity (Valid data of column parity is lower 6-bit in upper 2 bytes) If XOR data equals “0”, it will terminate normally because the ECC code is the...
  • Page 30 TMP92CH21 3.21.5 Download with UART (1) Connection example Figure 3.21.8 shows an example of UART. (A 16-bit NOR flash is used as program memory.) UART 3 pins TXD1, PF0 (output) Level RXD1, PF1 (input) P82, shifter P70, PJ2, SRWR TMP92CH21 NOR flash D0 to D15 D0 to D15...
  • Page 31 TMP92CH21 (3) UART data transfer format Table 3.21.7 to Table 3.21.12 show the supported frequency, data transfer format, baud rate modification commands, operation commands, version management information, and frequency measurement result with data storing location, respectively. Please also refer to the description of boot program operation in the following pages. Table 3.21.7 Supported Frequency (f OSCH 6.00...
  • Page 32 TMP92CH21 Table 3.21.9 Baud Rate Modification Command Baud Rate (bps) 9600 19200 38400 57600 115200 Modification Command Note 1:If f is either 16.0, 20.0, 20.58 or 25.0 MHz, 115200 bps is not supported. OSCH Note 2: If f is 10.0 MHz, both 57600 and 115200 bps are not supported. OSCH Note 3: If f is 6.00, 8.00 or 9.00 MHz, then 38400, 57600 and 115200 bps are not...
  • Page 33 TMP92CH21 The seventh byte is used to send information of the measured frequency. The PC should check that the frequency of the resonator is measured correctly. The receive data in the eighth byte is the baud rate modification data. The five kinds of baud rate modification data shown in Table 3.21.9 are available.
  • Page 34 TMP92CH21 Error code The boot program sends the processing status to the PC using various codes. The error codes are listed in the table below. Table 3.21.13 Error Codes Error Code Meaning of Error Code Baud rate modification error occurred. Operation command error occurred.
  • Page 35 TMP92CH21 d) Notes on Intel Hex format (Binary) After receiving the checksum of a record, the device waits for the start mark (3AH for “ : ”) of the next record. Therefore, the device ignores all data received between records during that time unless the data is 3AH. Make sure that once the PC program has finished sending the checksum of the end record, it does not send anything and waits for 2 bytes of data to be received (upper and lower bytes of SUM).
  • Page 36 TMP92CH21 Error when receiving user program If the following errors occur in Intel Hex format when receiving the user program, the device goes to an idle state. When the record type is not 00H, 01H, and 02H When a checksum error occurs Error between frequency measurement and baud rate The boot program measures the resonator frequency when receiving matching data.

  • Page 37: Further Notes

    TMP92CH21 (5) Further notes Handshake function The TMP92CH21 has a pin, but boot programs do not use it. RS-232C connector When the boot program is running, do not connect or disconnect an RS-232C connector. Software on PC Special application software is needed on the PC. 2006-09-15 92CH21-454...
  • Page 38 TMP92CH21 3.21.6 Download with USB (1) Connection example Figure 3.21.9 shows an example of USB. (16-bit NOR flash is used as program memory.) PUCTL PC6, KO8, LDIV R4 = P82, 100 kΩ R1 = 1.5 kΩ P70, R2 = 27 Ω PJ2, SRWR D−...
  • Page 39 TMP92CH21 An outline flowchart is given below. (Legend) Control type Bulk type Host (PC) TMP92CH21 Transmit GET_DESCRIPTOR Recognition for connection Transmit DESCRIPTOR information Transmit MICON information command Preparing MICON Transmit MICON information data information data Confirming data Transmitting data Transmit MICON information command Converting Intel Hex format Preparing MICON...
  • Page 40 TMP92CH21 The vendor request command table is shown below. Table 3.21.16 Vendor Request Command Table Value of Command Name Outline Notes Request MICON (Microcomputer) This is transmitted after a setup Transmit information command stage is terminated by bulk in microcomputer transfer type.
  • Page 41 TMP92CH21 The standard request command table is shown below. Table 3.21.18 The Standard Request Command Table Standard Request Response Medthod By hardware, GET_STATUS automatically CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DISCRIPTOR Not supported SET_DISCRIPTOR By hardware, GET_CONFIGRATION automatically SET_CONFIGRATION GET_INTERFACE SET_INTERFACE Ignored SYNCH_FRAME The information transmitted by GET_DISCRIPTOR is shown below.
  • Page 42 TMP92CH21 Configuration Descriptor Field Name Value Meaning bLength 9 bytes Configuration descriptor bDescriptorType Total length (32 bytes) in which each descriptor wTotalLength 0020H of configuration descriptor, interface and endpoint is added. Interface is 1 bNumInterfaces Configuration number 1 bConfigurationValue Index value of string descriptor in which this iConfiguration configuration name is shown (Not used).
  • Page 43 TMP92CH21 The information transmitted by the MICON information command is shown below. Table 3.21.20 Information Transmitted by MICON Information Command Micon Information ASCII Code “TMP92CH21FG” 54H, 4DH, 50H, 39H, 32H, 43H, 48H, 32H, 31H, 46H, 47H, 20H, 20H, 20H, 20H The information transmitted by the result information command is shown below.
  • Page 44 TMP92CH21 (3) Description of USB boot program operation The boot program provides the following RAM loader function. The data, which is transmitted by the PC in Intel Hex format, is loaded to the internal RAM. After loading normally, the user program will begin to execute. The first received address is set as the starting address.
  • Page 45 TMP92CH21 Notes on user program format (Binary) After receiving the checksum of a record, the device waits for the start mark (3AH for “: ”) of the next record.The device therefore ignores all data received between records during that time unless the data is 3AH. The first record type is not needed as an address record because the initial value of the address pointer is 00H.
  • Page 46 TMP92CH21 (4) Further notes USB connector When the boot program is running, do not connect or disconnect the USB connector. Software on PC Special USB device driver and application software is needed on the PC. 2006-09-15 92CH21-463...

  • Page 47: Electrical Characteristics

    TMP92CH21 Electrical Characteristics Maximum Ratings Parameter Symbol Rating Unit −0.5 to 4.0 Power Supply Voltage −0.5 to VCC + 0.5 Input Voltage Output Current −2 Output Current Σ I Output Current (Total) Σ I −80 Output Current (Total) Power Dissipation (Ta = 85°C) °C Soldering Temperature (10 s) SOLDER...

  • Page 48: Dc Electrical Characteristics

    TMP92CH21 DC Electrical Characteristics (1/2) = 3.3 ± 0.3V/X1 = 6 to 40 MHz/Ta = −20 to 70°C = 2.7 − 3.6V/X1 = 6 to 27 MHz/Ta = −20 to 70°C Parameter Symbol Typ. Unit Condition X1 = 6 to 40 MHz Power supply voltage XT1 = 30 to 34 kHz (DVCC = AVCC)
  • Page 49 TMP92CH21 DC Electrical Characteristics (2/2) Parameter Symbol Typ. Unit Condition = 1.6 mA Output low voltage 0.45 = −400 μA Output high voltage 0.9 × V = −20 μA = 6.6 mA Output low voltage for = 3.0 to 3.6 V OL (T) OL (T) MX, MY pins...
  • Page 50 TMP92CH21 AC Characteristics 4.3.1 Basic Bus Cycle Read cycle Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit 1 OSC period (X1/X2) 166.7 27.7 37.0 2 System clock period ( = T) 333.3 55.5 74.0 0.5 T − 15 3 SDCLK low width 12.7 0.5 T −...
  • Page 51 TMP92CH21 (1) Read cycle (0 waits) SDCLK WAIT A0~A23 D0~D31 Data input SRxxB SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The above timing chart is an example. 2006-09-15 92CH21-468...
  • Page 52 TMP92CH21 (2) Write cycle (0 waits) SDCLK WAIT A0~A23 WRxx D0~D31 Data output SRxxB SRWR Note: The phase relation between X1 input signal and the other signals is undefined. The above timing chart is an example. 2006-09-15 92CH21-469...
  • Page 53 TMP92CH21 (3) Read cycle (1 wait) SDCLK WAIT A0 to A23 D0 to D31 Data input (4) Write cycle (1 wait) SDCLK WAIT A0 to A23 WRxx D0 to D31 Data output 2006-09-15 92CH21-470...
  • Page 54 TMP92CH21 Page ROM Read Cycle 4.3.2 (1) 3-2-2-2 mode Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit 1 System clock period ( = T) 166.7 55.5 2 A0, A1 → D0 to D31 input 2.0T − 50 3 A2 to A23 → D0 to D31 input 3.0T −...
  • Page 55 TMP92CH21 SDRAM Controller AC Characteristics 4.3.3 Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit 1 Ref/active to ref/active command period 2 Active to precharge command period 12210 3 Active to read/write command delay 55.5 time 4 Precharge to active command period 55.5 5 Active to active command period 166.5...
  • Page 56 TMP92CH21 (1) SDRAM read timing (CPU access or LCDC normal access) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE 16-bit data bus A1 to A10 Column Column A12 to A15 Column D0 to D15 Data input 32-bit data bus A1 to A11 Column Column A13 to A15...
  • Page 57 TMP92CH21 (2) SDRAM write timing (CPU access) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE 16-bit data bus A1 to A12 Column Column A12 to A15 Column D0 to D15 Data output 32-bit data bus A1 to A11 Column Column A13 to A15 Column D0 to D31 Data output...
  • Page 58 TMP92CH21 (3) SDRAM burst read timing (Start of burst cycle) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A1 to A11 or Column A1 to A10 A12 or A11 Column A13 to A15 or A12 to A15 D0 to D31 Data input Data input Data input 2006-09-15...
  • Page 59 TMP92CH21 (4) SDRAM burst read timing (End of burst cycle) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A1 to A11 or Column Column A1 to A10 A12 or A11 Column Column A13 to A15 or Column A12 to A15 D0 to D31 Data input Data input Data input...
  • Page 60 TMP92CH21 (5) SDRAM initialize timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A1 to A12 A20 to A23 (BS0 and BS1) 2006-09-15 92CH21-477...
  • Page 61 TMP92CH21 (6) SDRAM refresh timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE (7) SDRAM self refresh timing SDCLK SDCKE SDxxDQM SDCS SDRAS SDCAS SDWE 2006-09-15 92CH21-478...
  • Page 62 TMP92CH21 NAND Flash Controller AC Characteristics 4.3.4 Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit (1 + n) T − 12 low width 43.5 NDRE (1 + n) T − 25 − data access time 30.5 NDRE REA (3.0 V) (1 + n) T −...

  • Page 63: Interrupt Operation

    TMP92CH21 Serial Channel Timing 4.3.5 (1) SCLK input mode (I/O interface mode) Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit μs SCLK cycle 0.888 1.184 Output data → SCLK rising/falling /2 − 4T − 110 SCLK rising/falling → Output data hold /2 + 2T + 0 SCLK rising/falling →...
  • Page 64 TMP92CH21 4.3.7 LCD Controller (SR mode) Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit LCP0 clock period ( = tm) 0.5 tm − 12 LCP0 high width 43.5 0.5 tm − 12 LCP0 low width 43.5 Data valid → LCP0 falling 0.5 tm −...
  • Page 65 TMP92CH21 S Timing (I S, SIO Mode) 4.3.8 Variable Parameter Symbol 40 MHz 36 MHz 27 MHz Unit I2SCKO clock period − 15 I2SCKO high width 0.5 t − 15 I2SCKO low width 0.5 t − 15 I2SDO, I2SWS setup time 0.5 t −...

  • Page 66: Ad Conversion Characteristics

    TMP92CH21 AD Conversion Characteristics Parameter Symbol Typ. Unit − 0.2 Analog reference voltage (+) REFH + 0.2 Analog reference voltage (−) REFL AD converter power supply voltage AD converter ground Analog input voltage REFL REFH Analog current for analog reference voltage 1.35 <VREFON>...

  • Page 67: Connection Example

    TMP92CH21 Recommended Oscillation Circuit The TMP92CH21 has been evaluated by the oscillator vender below. Use this information when selecting external parts. Note: The total load value of the oscillator is the sum of external loads (C1 and C2) and the floating load of the actual assembled board.
  • Page 68 TMP92CH21 (3) Recommended ceramic oscillator: TDK Co., Ltd. Parameter of Elements Running Condition Oscillation Frequency Oscillator Product Number Voltage [°C] [MHZ] [pF] [pF] [Ω] [Ω] − − − − FCR4.0MC5 4.00 − − − − FCR6.0MC5 6.00 − − − −...

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