Toshiba TLCS-900/H1 Series Manual page 52

(4) Detailed description of the transfer mode register
0 0 0 Mode
DMAMn[4:0]
0 0 0 z z Destination INC mode
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
0 0 1 z z Destination DEC mode
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
0 1 0 z z Source INC mode
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
0 1 1 z z Source DEC mode
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
1 0 0 z z Source and destination INC mode
(DMADn+) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
1 0 1 z z Source and destination DEC mode
(DMADn−) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
1 1 0 z z Source and destination Fixed mode
(DMADn) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
1 1 1 0 0 Counter mode
DMASn ← DMASn + 1
DMACn ← DMACn − 1
If DMACn = 0 then INTTCn
00 = 1-byte transfer
ZZ:
01 = 2-byte transfer
10 = 4-byte transfer
11 = (Reserved)
Note1: N stands for the micro DMA channel number (0 to 7)
DMADn+/DMASn+: Post-increment (register value is incremented after transfer)
DMADn−/DMASn−: Post-decrement (register value is decremented after transfer)
"I/O" signifies fixed memory addresses; "memory" signifies incremented or decremented memory
addresses.
Note2: The transfer mode register should not be set to any value other than those listed above.
Note3: The execution state number shows number of best case (1-state memory access).
DMAM0 to DMAM7
Mode Description
92CH21-50
TMP92CH21
Execution
State Number
5 states
5 states
5 states
5 states
6 states
6 states
5 states
5 states
2009-06-19