Toshiba TLCS-900/H1 Series Manual page 362

Relation of memory map image and output data
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Address 0
LSB
D0
0 1 2 3 4 5 6
R1 G1
Address 4
LSB
D0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
R5 G5
LD bus output sequence
8 bits (TFT)
0 (R1) → 8 (R2)
LD0
1 (R1) → 9 (R2)
LD1
2 (R1) → 10 (R2) ...
LD2
3 (G1) → 11 (G2) ...
LD3
4 (G1) → 12 (G2) ...
LD4
5 (G1) → 13 (G2) ...
LD5
6 (B1) → 14 (B2) ...
LD6
7 (B1) → 15 (B2) ...
LD7
* When using 256-color TFT mode, 8-bit LD bus width must be used.
LD8, LD9, LD10 and LD11 terminals are available for use as general ports.
Figure 3.14.15 Relation of Memory Map Image and Output Data (5)
256 colors (8 bpp; R: 3 bits, G: 3 bits, B: 2 bits)
Display memory image
Address 1
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
B1 R2 G2
Address 5
B5 R6 G6
...
...
92CH21-360
Address 2
B2 R3 G3
Address 6
B6 R7 G7
TMP92CH21
Address 3
B3
R4 G4
Address 7
B7
R8 G8
2009-06-19
MSB
D31
B4
MSB
D31
B8