Toshiba TLCS-900/H1 Series Manual page 398

3.17.2 Block Diagram
NAND-Flash Controller Channel 0 (NDFC0)
Internal bus
bus I/F
Register
address
Host I/F
timing
control
NAND-Flash Controller Channel 1 (NDFC1)
Registers
NAND-Flash
I/F timing
control
(Same as NDFC0 )
NDCR<CHSEL> register
Figure 3.17.1 NAND-Flash Controller Block Diagram
92CH21-396
ND_CE*
ND_ALE
ND_CLE
ND_RE*
ND_WE*
ND_RB*
DATA_OUT [7:0]
DATA_IN [7:0]
D Q
TMP92CH21
ND 0 CE
A
Y
NDCLE,
B
NDALE,
,
NDRE
S
,
NDWE
D7 to D0
D7 to D0,
NDR/ B
ND 1 CE
2009-06-19