Toshiba TLCS-900/H1 Series Manual page 214

3.10.3.12 DATASET Register
data or not.
which corresponds to the applicable endpoint is set to "1" and an interrupt generated.
And, when the application reads the 1-packet data, this bit is cleared to "0". In
transmit status, when it has completed the 1-packet data transfer to FIFO, this bit is
set to "1". And when valid data is transferred to the USB host, this bit is cleared to "0"
and an interrupt generated.
DATASET1
bit Symbol
(07CCH)
Read/Write
Reset State
DATASET2
bit Symbol
(07CDH)
Read/Write
Reset State
Note: DATASET1<EP3_DSET_B>, DATASET2 registers are not used in the TMP92CH21.
This register shows whether FIFO contains data or not.
The application program can access this register to check whether FIFO contains
In receive status, when a valid data transfer from the USB host has finished, the bit
7 6
EP3_DSET_B EP3_DSET_A EP2_DSET_B
R R
0 0
7 6
EP7_DSET_B EP7_DSET_A EP6_DSET_B
R R
0 0
•
Single packet mode
(DATASET1: Bit0, bit2, bit4 and bit6
These bits show whether FIFO of the corresponding endpoint has data or not.
In receive mode endpoint, if the corresponding endpoint bit is "1", FIFO
contains data to be read. Access EPx_SIZE register, determine the size of the
data that should be read, and read data of this size. When this bit is "0", there is
no data to be read.
In transmit mode endpoint, if the corresponding endpoint bit is "0", the CPU
can transfer data under the FIFO payload. If this bit is "1", because FIFO has
transfer data waiting, transfer data to FIFO from UDC after the corresponding
bit has been cleared to "0". When a short-packet is transferred, access EOP
register after writing transmission data to the corresponding endpoint.
• Dual packet mode
(DATASET1: Bit3, bit5 and bit7
These bits become effective in the dual packet mode. FIFO has 2-packets in
this mode.
Each packet (packet-A and packet-B) has its own DATASET-bit.
Unlike as in the case above, in isochronous transfer, this shows the packet that
can access the current frame. In this case, whether bit A or B is set to "1", it is
renewed according to the shifting frame.
5 4
EP2_DSET_A EP1_DSET_B EP1_DSET_A
R R
0 0
5 4
EP6_DSET_A EP5_DSET_B EP5_DSET_A EP4_DSET_B EP4_DSET_A
R R
0 0
DATASET2: Bit0, bit2, bit4 and bit6)
DATASET2: Bit1, bit3 bit5 and bit7)
92CH21-212
TMP92CH21
3 2 1
R R
0 0
3 2 1
R R R
0 0 0
0
EP0_DSET_A
R
0
0
R
0
2009-06-19