Toshiba TLCS-900/H1 Series Manual page 200

bit Symbol
USBINTFR2
(07F1H) Read/Write
Reset State
Function
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
bit Symbol
USBINTFR3
(07F2H)
Read/Write
Reset State
Function
Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.)
Note: The EPx_FULL_A/B and EPx_Empty_A/B flags are not status flags. Therefore, check DATASET register to
7 6
EP1_FULL_A EP1_Empty_A EP1_FULL_B
R/W R/W
0 0
When read 0: Not generate interrupt
7 6
EP3_FULL_A EP3_Empty_A
R/W R/W
0 0
When read 0:Not generate
interrupt
1:Generate
interrupt
When write 0: Clear flag
−
1:
• EPx_FULL_A/B:
(When transmitting)
This is set to "1" when CPU full writes data to FIFO_A/B.
(When receiving)
This is set to "1" when UDC full receives data to FIFO_A/B.
• EPx_Empty_A/B:
(When transmitting)
This is set to "1" when FIFO becomes empty after transmission.
(When receiving)
This is set to "1" when FIFO becomes empty after CPU reads all data from FIFO.
determine if FIFO-status is needed.
5 4 3
EP1_Empty_B EP2_FULL_A
R/W R/W R/W
0 0 0
When write 0: Clear flag
1: Generate interrupt
5 4 3
92CH21-198
TMP92CH21
2 1
EP2_Empty_A EP2_FULL_B EP2_Empty_B
R/W R/W
0 0
1: −
2 1
2009-06-19
0
R/W
0
0