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Toshiba TLCS-870/C Series Manual
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Toshiba TLCS-870/C Series Manual

Toshiba TLCS-870/C Series Manual

8 bit microcontroller
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8 Bit Microcontroller
TLCS-870/C Series
TMP86FH09NG
　　　　　　　　　　　　　　　November 10, 2005

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Summary of Contents for Toshiba TLCS-870/C Series

  • Page 1 8 Bit Microcontroller TLCS-870/C Series TMP86FH09NG 　　　　　　　　　　　　　　　November 10, 2005...
  • Page 2 It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
  • Page 3 • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patent or patent rights of TOSHIBA or others.
  • Page 4 tentative 1.1 Features TMP86FH09NG 11. 10-bit successive approximation type AD converter - Analog inputs: 6ch 12. Key On Wake Up : 4ch 13. Clock operation Single clock mode Dual clock mode 14. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock...
  • Page 5 tentative TMP86FH09NG 1.2 Pin Assignment P-SDIP32-400-1.78 P37 (AIN5/STOP5) P36 (AIN4/STOP4) XOUT P35 (AIN3/STOP3) TEST P34 (AIN2/STOP2) (VAREF/AVDD) VDD P33 (AIN1) (XTIN) P21 P32 (AIN0) (XTOUT) P22 P31 (TC4/ PDO4 PWM4 PPG4 RESET P30 (TC3/ PDO3 PWM3 ) P20 STOP INT5 P12 ( (TXD) P00 P11 (...
  • Page 6 tentative 1.3 Block Diagram TMP86FH09NG 1.3 Block Diagram Program memory Address/data bus (Flash memory) TLCS-870/C Data memory Boot program Flash memory I/F (RAM) (ROM) Standby control Interrupt controller circuit RESET System control circuit TEST Time base Timing generator 16-bit 8-bit Serial timer 8-bit AD...
  • Page 7 tentative TMP86FH09NG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86FH09NG memory is composed Flash, RAM SFR (Special function register) and DBR(Data buffer register).
  • Page 8 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to “00H”. (TMP86FH09NG) HL, 0040H ;...
  • Page 9 tentative TMP86FH09NG Low-frequency clock High-frequency clock XOUT XOUT XTIN XTIN XTOUT XTOUT (Open) (Open) (c) Crystal (d) External oscillator (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program.
  • Page 10 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1.
  • Page 11 The minimum instruction execution unit is called an “machine cycle”. There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
  • Page 12 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> = "1", and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs.
  • Page 13 tentative TMP86FH09NG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. IDLE2 mode In this mode, the internal oscillation circuit remain active.
  • Page 14 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG IDLE0 RESET Reset release mode Note 2 SYSCR2<TGHALT> = "1" SYSCR2<IDLE> = "1" SYSCR1<STOP> = "1" IDLE1 NORMAL1 mode mode Interrupt STOP pin input (a) Single-clock mode SYSCR2<XTEN> = "0" SYSCR2<XTEN> = "1" SYSCR2<IDLE>...
  • Page 15 tentative TMP86FH09NG System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN (Initial value: 0000 000*) 0: CPU core and peripherals remain active STOP STOP mode start 1: CPU core and peripherals are halted (Start STOP mode) Release method for STOP 0: Edge-sensitive release RELM mode...
  • Page 16 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG 2.2.4 Operating Mode Control 2.2.4.1 STOP mode STOP mode is controlled by the system control register 1, the pin input and key-on wakeup input STOP (STOP5 to 2) which is controlled by the STOP mode release control register (STOPCR). pin is also used both as a port P20 and an (external interrupt input 5) pin.
  • Page 17 tentative TMP86FH09NG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if F, SINT5 port P20 is at high (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. ;...
  • Page 18 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low- frequency clock oscillator is turned on.
  • Page 19 tentative TMP86FH09NG Figure 2-9 STOP Mode Start/Release Page 19...
  • Page 20 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate.
  • Page 21 tentative TMP86FH09NG • Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode.
  • Page 22 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 22...
  • Page 23 tentative TMP86FH09NG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1.
  • Page 24 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG • Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2<TGHALT> to “1”. • Release the IDLE0 and SLEEP0 modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode.
  • Page 25 tentative TMP86FH09NG Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 25...
  • Page 26 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2<SYSCK>...
  • Page 27 tentative TMP86FH09NG Switching from SLOW1 mode to NORMAL2 mode Note: After SYSCK is cleared to “0”, executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms).
  • Page 28 tentative 2. Operational Description 2.2 System Clock Controller TMP86FH09NG Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 28...
  • Page 29 tentative TMP86FH09NG 2.3 Reset Circuit The TMP86FH09NG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset.
  • Page 30 tentative 2. Operational Description 2.3 Reset Circuit TMP86FH09NG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be generated.
  • Page 31 tentative TMP86FH09NG Page 31...
  • Page 32 tentative 2. Operational Description 2.3 Reset Circuit TMP86FH09NG Page 32...
  • Page 33 tentative TMP86FH09NG 3. Interrupt Control Circuit The TMP86FH09NG has a total of 17 interrupt sources excluding reset, of which 1 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable.
  • Page 34 tentative 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86FH09NG Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0"...
  • Page 35 tentative TMP86FH09NG Example 1 :Enables interrupts individually and sets IMF ← ; IMF ← (EIRL), 1110100010100000B ; EF15 to EF13, EF11, EF7, EF5 Note: IMF should not be set. ← ; IMF Example 2 :C compiler description example unsigned int _io (3AH) EIRL; /* 3AH shows EIRL address */ _DI();...
  • Page 36 tentative 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86FH09NG Interrupt Latches (Initial value: 0000000 000000**) ILH,ILL (003DH, 003CH) IL15 IL14 IL13 IL12 IL11 IL10 ILH (003DH) ILL (003CH) at RD at WR IL15 to IL2 Interrupt latches 0: No interrupt request 0: Clears the interrupt request 1: (Interrupt latch is not set.) 1: Interrupt request...
  • Page 37 tentative TMP86FH09NG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register.
  • Page 38 tentative 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86FH09NG Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
  • Page 39 tentative TMP86FH09NG Address (Example) At acceptance of At execution of At execution of At execution of an interrupt PUSH instruction POP instruction RETI instruction 3.4.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: (GSAVA), A...
  • Page 40 tentative 3. Interrupt Control Circuit 3.5 Software Interrupt (INTSW) TMP86FH09NG As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively.
  • Page 41 tentative TMP86FH09NG 3.6 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen- erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter- rupt is in process.
  • Page 42 tentative 3. Interrupt Control Circuit 3.8 External Interrupts TMP86FH09NG Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "sig- nal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the pin input.
  • Page 43 tentative TMP86FH09NG External Interrupt Control Register EINTCR (0037H) INT1NC INT0EN INT3ES INT4ES INT1ES (Initial value: 0000 000*) 0: Pulses of less than 63/fc [s] are eliminated as noise INT1NC Noise reject time select 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P10 input/output port INT0EN P10/...
  • Page 44 tentative 3. Interrupt Control Circuit 3.8 External Interrupts TMP86FH09NG Page 44...
  • Page 45 tentative TMP86FH09NG 4. Special Function Register (SFR) The TMP86FH09NG adopts the memory mapped I/O system, and all peripheral control and data transfers are per- formed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
  • Page 46 tentative 4. Special Function Register (SFR) 4.1 SFR TMP86FH09NG Address Read Write 0026H UARTCR2 ― 0027H RDBUF TDBUF 0028H SESR – 0029H SEDR 002AH SECR 002BH Reserved 002CH Reserved 002DH Reserved 002EH Reserved 002FH Reserved 0030H Reserved 0031H STOPCR ― 0032H Reserved 0033H...
  • Page 47 tentative TMP86FH09NG 4.2 DBR Address Bit7 to Bit4 Bit3 to Bit0 0F80H Reserved 0FE8H Reserved 0FE9H FLSSTB ― 0FEAH SPCR 0FEBH Reserved 0FFEH Reserved 0FFFH FLSCR Note 1: Do not access reserved areas by the program. Note 2: － ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc.
  • Page 48 tentative 4. Special Function Register (SFR) 4.1 SFR TMP86FH09NG Page 48...
  • Page 49 tentative TMP86FH09NG 5. I/O Ports The TMP86FH09NG have 4 parallel input/output ports as follows. Primary Function Secondary Functions Port P0 8-bit I/O port External interrupt input, Timer/Counter input/output, serial interface input/output Port P1 7-bit I/O port External interrupt input and divider output Port P2 3-bit I/O port External interrupt input and STOP mode release signal input...
  • Page 50 tentative 5. I/O Ports TMP86FH09NG 5.1 P0 (P07 to P00) Port (High Current) The P0 port is an 8-bit input/output port shared with external interrupt input, SEI serial interface input/output, and UART and 16-bit timer counter input/output. When using this port as an input port or for external interrupt input, SEI serial interface input/output, or UART input/output, set the output latch to 1.
  • Page 51 tentative TMP86FH09NG 5.2 P1 (P16 to P10) Port The P1 port is a 7-bit input/output port that can be specified for input or output bitwise. The P1 Port Input/output Control Register (P1CR) is used to specify this port for input or output. When reset, the P1CR register is initialized to 0, with the P1 port set for input mode.
  • Page 52 tentative 5. I/O Ports TMP86FH09NG 5.3 P2 (P22 to P20) Port The P2 port is a 3-bit input/output port shared with external interrupt input, STOP canceling signal input, and low- frequency resonator connecting pin. When using this port as an input port or function pin, set the output latch to 1. The output latch is initialized to 1 when reset.
  • Page 53 tentative TMP86FH09NG 5.4 P3 (P37 to P30) Port The P3 port is an 8-bit input/output port that can be specified for input or output bitwise, and is shared with analog input, key-on wakeup input, and 8-bit timer counter input/output. The P3 Port Input/output Control Register (P3CR) and ADCCR1<AINDS>...
  • Page 54 tentative 5. I/O Ports TMP86FH09NG P3DR AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 (0003H) STOP5 STOP4 STOP3 STOP2 (Initial value: 0000 0000) PDO4 PDO3 PWM4 PWM3 PPG4 P3CR (000AH) (Initial value: 0000 0000) Controls P3 port output (speci- 0: Input mode P3CR fied bitwise) 1: Output mode...
  • Page 55 tentative TMP86FH09NG 6. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 6.1 Time Base Timer 6.1.1 Configuration fc/2 or fs/2 fc/2 or fs/2 fc/2 or fs/2 IDLE0, SLEEP0...
  • Page 56 tentative 6. Time Base Timer (TBT) 6.1 Time Base Timer TMP86FH09NG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be per- formed simultaneously.
  • Page 57 tentative TMP86FH09NG 6.2 Divider Output ( Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from pin. 6.2.1 Configuration Output latch Data output DVO pin fc/2 or fs/2 fc/2 or fs/2 fc/2...
  • Page 58 tentative 6. Time Base Timer (TBT) 6.2 Divider Output (DVO) TMP86FH09NG Example :1.95 kHz pulse output (fc = 16.0 MHz) ; DVOCK ← "00" (TBTCR) , 00000000B ; DVOEN ← "1" (TBTCR) , 10000000B Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode...
  • Page 59 tentative TMP86FH09NG 7. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as “reset request”...
  • Page 60 tentative 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86FH09NG 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below.
  • Page 61 tentative TMP86FH09NG Watchdog Timer Control Register 1 WDTCR1 (0034H) (ATAS) (ATOUT) WDTEN WDTT WDTOUT (Initial value: **11 1001) 0: Disable (Writing the disable code to WDTCR2 is required.) Write WDTEN Watchdog timer enable/disable 1: Enable only NORMAL1/2 mode SLOW1/2 mode DV7CK = 0 DV7CK = 1 Watchdog timer detection time...
  • Page 62 tentative 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86FH09NG 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1.
  • Page 63 tentative TMP86FH09NG 7.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the internal hardware is reset. The reset time is 8/fc to 24/fc [s] (0.5 to 1.5 µs @ fc = 16.0 MHz). Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is 8/fc to 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted.
  • Page 64 tentative 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86FH09NG 7.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) ATAS ATOUT (WDTEN) (WDTT) (WDTOUT)
  • Page 65 tentative TMP86FH09NG 7.3.4 Address Trap Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, an address trap reset request is generated. When an address trap reset request is generated, the internal hardware is reset. The reset time is 8/fc to 24/fc [s] (0.5 to 1.5 µs @ fc = 16.0 MHz). Note:When an address trap reset is generated in the SLOW1 mode, the reset time is 8/fc to 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted.
  • Page 66 tentative 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86FH09NG Page 66...
  • Page 67 tentative TMP86FH09NG 8. 16-Bit TimerCounter 1 (TC1) 8.1 Configuration Figure 8-1 TimerCounter 1 (TC1) Page 67...
  • Page 68 tentative 8. 16-Bit TimerCounter 1 (TC1) 8.2 TimerCounter Control TMP86FH09NG 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register TC1DRAH (0011H) TC1DRAL (0010H) TC1DRA (0011H, 0010H) (Initial value: 1111 1111 1111 1111) Read/Write...
  • Page 69 tentative TMP86FH09NG Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other modes) Note 6: Set TFF1 to “0”...
  • Page 70 tentative 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FH09NG 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register 1A (TC1DRA) value is detected, an INTTC1 interrupt is generated and the up-counter is cleared.

  • Page 71: Table Of Contents

    tentative TMP86FH09NG Timer start Source clock n − 1 Counter TC1DRA Match detect Counter clear INTTC1 interruput request Timer mode Source clock m − 2 m − 1 n − 1 Counter m + 1 m + 2 n + 1 Capture Capture m −...
  • Page 72 tentative 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FH09NG 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge used to start counting, either the rising or falling edge is defined in TC1CR<TC1S>.
  • Page 73 tentative TMP86FH09NG At the rising edge (TC1S = 10) Count start Count start TC1 pin input Source clock n − 1 Up-counter TC1DRA Match detect Count clear INTTC1 interrupt request Trigger start (METT1 = 0) At the rising Count clear Count start Count start edge (TC1S = 10)
  • Page 74 tentative 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FH09NG 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the count up edge in TC1CR<TC1S>. When a match between the up-counter and the TC1DRA value is detected, an INTTC1 interrupt is generated and the up-counter is cleared.

  • Page 75: Counter

    tentative TMP86FH09NG 8.3.4 Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected.
  • Page 76 tentative 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FH09NG 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or falling edge of the internal clock is selected as the trigger edge in TC1CR<TC1S>.
  • Page 77 tentative TMP86FH09NG Example :Duty measurement (resolution fc/2 [Hz]) (INTTC1SW). 0 : INTTC1 service switch initial setting Address set to convert INTTC1SW at each INTTC1 (TC1CR), 00000110B : Sets the TC1 mode and source clock : IMF= “0” (EIRL). 7 : Enables INTTC1 : IMF= “1”...

  • Page 78: Capture

    tentative 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FH09NG Count start Count start TC1 pin input Trigger (TC1S = "10") Internal clock Counter n - 1 Capture TC1DRB INTTC1 interrupt request [Application] High-or low-level pulse width measurement (a) Single-edge capture (MCAP1 = "1") Count start Count start...
  • Page 79 tentative TMP86FH09NG 8.3.6 Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input pulse to the TC1 pin or the command start.
  • Page 80 tentative 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FH09NG Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs (fc = 16 MHz) Setting port (TC1CR), 10000111B : Sets the PPG mode, selects the source clock (TC1DRA), 007DH : Sets the cycle (1 ms ÷...
  • Page 81 tentative TMP86FH09NG Timer start Internal clock Counter n + 1 n + 1 TC1DRB Match detect TC1DRA PPG pin output INTTC1 interrupt request Note: m > n Continuous pulse generation (TC1S = 01) Count start TC1 pin input Trigger Internal clock Counter n + 1 TC1DRB...
  • Page 82 tentative 8. 16-Bit TimerCounter 1 (TC1) 8.3 Function TMP86FH09NG Page 82...
  • Page 83 tentative TMP86FH09NG 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration PWM mode Overflow INTTC4 interrupt request fc/2 or fs/2 Clear 8-bit up-counter fc/2 TC4S fc/2 fc/2 PDO, PPG mode Toggle fc/2 16-bit mode TC4 pin PDO4/PWM4/ 16-bit PPG4 pin mode Clear TC4M TC4S Timer F/F4...
  • Page 84 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (i001CH) (Initial value: 1111 1111) PWREG3 (i001EH) (Initial value: 1111 1111)
  • Page 85 tentative TMP86FH09NG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9- Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 85...
  • Page 86 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (i001DH) (Initial value: 1111 1111) PWREG4 (i001FH) (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running.
  • Page 87 tentative TMP86FH09NG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9-1 and Table 9-2.
  • Page 88 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) fc/2 Operating mode fc/2 fc/2 fc/2 fc/2 pin input pin input fs/2 Ο Ο Ο Ο 8-bit timer – –...
  • Page 89 tentative TMP86FH09NG Table 9-3 Constraints on Register Values Being Compared Operating mode Register Value 1≤ (TTREGn) ≤255 8-bit timer/event counter 1≤ (TTREGn) ≤255 8-bit PDO 8-bit PWM 2≤ (PWREGn) ≤254 1≤ (TTREG4, 3) ≤65535 16-bit timer/event counter 256≤ (TTREG4, 3) ≤65535 Warm-up counter 2≤...
  • Page 90 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG 9.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- bit timer.
  • Page 91 tentative TMP86FH09NG TC4CR<TC4S> Internal Source Clock Counter TTREG4 Match detect Counter clear Counter clear Match detect INTTC4 interrupt request Figure 9-2 8-Bit Timer Mode Timing Chart (TC4) 9.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTCCj interrupt is generated and the up-counter is cleared.
  • Page 92 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port ÷ ÷ (TTREG4), 3DH : 1/1024 2 = 3DH (TC4CR), 00010001B : Sets the operating clock to fc/2 , and 8-bit PDO mode.
  • Page 93 tentative TMP86FH09NG Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Page 93...
  • Page 94 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG 9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state.
  • Page 95 tentative TMP86FH09NG Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) Page 95...
  • Page 96 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG 9.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S>...
  • Page 97 tentative TMP86FH09NG 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR<TC4S>...
  • Page 98 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the 4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the pin during the warm-up period time after exiting the STOP mode.
  • Page 99 tentative TMP86FH09NG Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 99...
  • Page 100 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG 9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode.
  • Page 101 tentative TMP86FH09NG Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 101...
  • Page 102 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG 9.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCouter.
  • Page 103 tentative TMP86FH09NG 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, set SYSCR2<XEN> to 1 to oscillate the high-frequency clock. When a match between the up-counter and the timer register (TTREG4, 3) value is detected after the timer is started by setting TC4CR<TC4S>...
  • Page 104 tentative 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86FH09NG Page 104...
  • Page 105 tentative TMP86FH09NG 10. Asynchronous Serial interface (UART ) 10.1 Configuration UART control register 1 Transmit data buffer Receive data buffer UARTCR1 TDBUF RDBUF Shift register Parity bit Shift register Stop bit INTTXD Noise rejection circuit INTRXD Transmit/receive clock fc/2 fc/2 fc/2 fc/13 fc/26...
  • Page 106 tentative 10. Asynchronous Serial interface (UART ) 10.2 Control TMP86FH09NG 10.2 Control UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni- tored using the UART status register (UARTSR). UART Control Register1 UARTCR1 (0025H) STBT EVEN (Initial value: 0000 0000)
  • Page 107 tentative TMP86FH09NG UART Status Register UARTSR (0025H) PERR FERR OERR RBFL TEND TBEP (Initial value: 0000 11**) No parity error PERR Parity error flag Parity error No framing error FERR Framing error flag Framing error No overrun error OERR Overrun error flag Overrun error Read only...
  • Page 108 tentative 10. Asynchronous Serial interface (UART ) 10.3 Transfer Data Format TMP86FH09NG 10.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added to the transfer data.
  • Page 109 tentative TMP86FH09NG 10.4 Transfer Rate The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows. Table 10-1 Transfer Rate (Example) Source Clock 16 MHz 8 MHz 4 MHz 76800 [baud] 38400 [baud] 19200 [baud] 38400 19200...
  • Page 110 tentative 10. Asynchronous Serial interface (UART ) 10.6 STOP Bit Length TMP86FH09NG 10.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>. 10.7 Parity Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>. 10.8 Transmit/Receive Operation 10.8.1 Data Transmit Operation Set UARTCR1<TXE>...
  • Page 111 tentative TMP86FH09NG 10.9 Status Flag 10.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read after read- ing the UARTSR.
  • Page 112 tentative 10. Asynchronous Serial interface (UART ) 10.9 Status Flag TMP86FH09NG UARTSR<RBFL> RxD pin Stop Final bit xxxx0 Shift register xxx0 ** 1xxxx0 RDBUF yyyy UARTSR<FERR> After reading UARTSR then RDBUF clears OERR. INTRXD interrupt Figure 10-7 Generation of Overrun Error 10.9.4 Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full flag UARTSR<RBFL>...
  • Page 113 tentative TMP86FH09NG Data write Data write zzzz TDBUF xxxx yyyy ***** 1 1xxxx0 * 1xxxx **** 1x ***** 1 1yyyy0 Shift register TxD pin Start Bit 0 Final bit Stop UARTSR<TBEP> After reading UARTSR writing TDBUF clears TBEP. INTTXD interrupt Figure 10-9 Generation of Transmit Data Buffer Empty 10.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR<TBEP>...
  • Page 114 tentative 10. Asynchronous Serial interface (UART ) 10.9 Status Flag TMP86FH09NG Page 114...
  • Page 115 tentative TMP86FH09NG 11. Serial Expansion Interface (SEI) SEI is one of the serial interfaces incorporated in the TMP86FH09NG. It allows connection to peripheral devices via full-duplex synchronous communication protocols. The TMP86FH09NG contain one channel of SEI. SEI is connected with an external device through SCLK, MOSI, MISO and the terminal SS. SCLK, MOSI, MISO, pins respectively are shared with P02, P03, P04 and P05.
  • Page 116 tentative 11. Serial Expansion Interface (SEI) 11.2 SEI Operation TMP86FH09NG 11.2 SEI Operation During a SEI transfer, data transmission (serial shift-out) and reception (serial shift-in) are performed simulta- neously. The serial clock synchronizes the timing at which information on the two serial data lines are shifted or sampled.
  • Page 117 tentative TMP86FH09NG 11.3 SEI Pin Functions The TMP86FH09NG have four input/output pins associated with SEI transfer. The functionality of each pin depends on the SEI device’s mode (master or slave). The SCLK pin, MOSI pin and MISO pin of all SEI devices are connected with the same name pin to each other . 11.3.1 SCLK pin The SCLK pin functions as an output pin when SEI is set for master, or as an input pin when SEI is set for slave.
  • Page 118 tentative 11. Serial Expansion Interface (SEI) 11.4 SEI Transfer Formats TMP86FH09NG 11.4 SEI Transfer Formats The transfer formats are set using CPHA and CPOL (SECR<CPHA,CPOL>). CPHA allows transfer protocols to be selected between two. 11.4.1 CPHA (SECR register bit 2) = 0 format Figure 11-2 shows a transfer format where CPHA = 0.
  • Page 119 tentative TMP86FH09NG 11.4.2 CPHA = 1 format Figure 11-3 shows a transfer format where CPHA = 1. SCLK cycle SCLK (CPOL = 0) SCLK Internal (CPOL = 1) shift clock MOSI MISO Figure 11-3 Transfer Format where CPHA = 1 Table 11-4 Transfer Format Details where CPHA = 1 SCLK Level when Not Data Shift...
  • Page 120 tentative 11. Serial Expansion Interface (SEI) 11.5 Functional Description TMP86FH09NG 11.5 Functional Description Figure 11-4 shows how the SEI master and slave are connected. When the master device sends data from its MOSI pin to a slave device’s MOSI pin, the slave device returns data from its MISO pin to the master device’s MISO pin.
  • Page 121 tentative TMP86FH09NG 11.6 SEI Registers The SEI interface has the SEI Control Register (SECR), SEI Status Register (SESR), and SEI Data Register (SEDR) which are used to set up the SEI system and enable/disable SEI operation. 11.6.1 SEI Control Register (SECR) MODE MSTR CPOL...
  • Page 122 tentative 11. Serial Expansion Interface (SEI) 11.6 SEI Registers TMP86FH09NG Slave mode When the SEI is operating as a slave, the serial clock is input from the master and the setting of the SER bit has no effect. The maximum transfer rate is fc/4. Note: Take note of the following relationship between the serial clock speed and fc on the master side: 15.625 kbps <...
  • Page 123 tentative TMP86FH09NG 11.7 Interrupt Generation The SEI for the TMP86FH09NG uses INTSEI1. When the SESR<SEF> changes state from “0” to “1”, respective interrupts is generated. Table 11-6 SEI Interrupt SEI interrupt channel 1 (INTSEI1) Interrupt generated for SEF 11.8 SEI System Errors The SEI has the facility to detect following two system errors.
  • Page 124 tentative 11. Serial Expansion Interface (SEI) 11.9 Bus Driver Protection TMP86FH09NG Input/output Control Register. In this case, these pins must be provided with pull-up resistors external to the chip. • When using the SEI pins as CMOS outputs, we recommend connecting them to the bus via resistors in order to protect the device against collision of drivers.
  • Page 125 tentative TMP86FH09NG 12. 10-bit AD Converter (ADC) The TMP86FH09NG have a 10-bit successive approximation type AD converter. 12.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 12-1. It consists of control register ADCCR1 and ADCCR2, converted value register ADCSR1 and ADCDR2, a DA converter, a sample-hold circuit, a comparator, and a successive comparison circuit.
  • Page 126 tentative 12. 10-bit AD Converter (ADC) 12.2 Register configuration TMP86FH09NG 12.2 Register configuration The AD converter consists of the following four registers: 1. AD converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to per- form AD conversion and controls the AD converter as it starts operating.
  • Page 127 tentative TMP86FH09NG AD Converter Control Register 2 ADCCR2 (000FH) IREFON "1" "0" (Initial value: **0* 000*) DA converter (Ladder resistor) connection Connected only during AD conversion IREFON control Always connected 000: Reserved 001: Reserved 010: 78/fc AD conversion time select 011: 156/fc (Refer to the following table about the con-...
  • Page 128 tentative 12. 10-bit AD Converter (ADC) 12.2 Register configuration TMP86FH09NG Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: The ADCDR2<ADBF> is set to "1" when AD conversion starts, and cleared to "0" when AD conversion finished. It also is cleared upon entering STOP mode .
  • Page 129 tentative TMP86FH09NG 12.3 Function 12.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD conversion, the conversion result is stored in AD converted value registers (ADCDR1, ADCDR2) and at the same time ADCDR2<EOCF>...
  • Page 130 tentative 12. 10-bit AD Converter (ADC) 12.3 Function TMP86FH09NG ADCCR1<AMD> “11” “00” AD conversion start ADCCR1<ADRS> AD convert operation suspended. 1st conversion Conversion operation Conversion result is not stored. 2nd conversion result 3rd conversion result result Indeterminate ADCDR1,ADCDR2 1st conversion result 2nd conversion result 3rd conversion result ADCDR2<EOCF>...
  • Page 131 tentative TMP86FH09NG Example :After selecting the conversion time 19.5 µs at 16 MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store the upper 8 bits in address 0009FH in RAM.
  • Page 132 tentative 12. 10-bit AD Converter (ADC) 12.5 Analog Input Voltage and AD Conversion Result TMP86FH09NG 12.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 12-4. conversion result 1024...
  • Page 133 Therefore, make sure the out- put impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capac- itor external to the chip.
  • Page 134 tentative 12. 10-bit AD Converter (ADC) 12.6 Precautions about AD Converter TMP86FH09NG Page 134...
  • Page 135 tentative TMP86FH09NG 13. Key-on Wakeup (KWU) TMP86FH09NG have fore pins P34 to P37, in addition to the P20 ( ) pin, that can be used to exit STOP INT5 STOP mode. When using these P34 to P37 pin’s input to exit STOP mode, pay attention to the logic of P20 pin. In details, refer to the following section"...
  • Page 136 tentative 13. Key-on Wakeup (KWU) 13.2 Control TMP86FH09NG 13.2 Control The P34 to P37 (STOP2 to STOP5) pins can individually be disabled/enabled using Key-on Wakeup Control Reg- ister (STOPCR). Before these pins can be used to place the device out of STOP mode, they nust be set for input using the P3 Port Input/Output Register (P3CR), P3Port Output Latch (P3DR), AD Control Register (ADCCR1).
  • Page 137 The parallel PROM mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. High-speed access to the flash memory is available by control- ling address and data signals directly. For the support of the program writer, please ask Toshiba sales rep- resentative.
  • Page 138 tentative 14. Flash Memory 14.1 Flash Memory Control TMP86FH09NG 14.1 Flash Memory Control The flash memory is controlled via the flash memory control register (FLSCR) and flash memory stanby control resister (FLSSTB). Flash Memory Control Register FLSCR (0FFFH) FLSMD (Initial value : 1100 ****) 1100: Disable command sequence execution Flash memory command sequence exe- FLSMD...
  • Page 139 tentative TMP86FH09NG 1. Transfer the control program of the FLSSTB register to the RAM area. 2. Jump to the RAM area. 3. Disable (DI) the interrupt master enable flag (IMF = “0”). 4. Set FLSSTB<FSTB> to “1”. 5. Execute the user program. 6.
  • Page 140 tentative 14. Flash Memory 14.2 Command Sequence TMP86FH09NG 14.2 Command Sequence The command sequence in the MCU and the serial PROM modes consists of six commands (JEDEC compatible), as shown in Table 14-1. Addresses specified in the command sequence are recognized with the lower 12 bits (excluding BA, SA, and FF7FH used for read protection).
  • Page 141 tentative TMP86FH09NG 14.2.3 Chip Erase (All Erase) This command erases the entire flash memory in approximately 30 ms. The next command sequence cannot be executed until the erase operation is completed. To check the completion of the erase operation, perform read operations repeatedly for data polling until the same data is read twice from the same address in the flash memory.
  • Page 142 tentative 14. Flash Memory 14.3 Toggle Bit (D6) TMP86FH09NG 14.3 Toggle Bit (D6) After the byte program, chip erase, and read protect command sequence is executed, any consecutive attempts to read from the same address is reversed bit 6 (D6) of the data (toggling between 0 and 1) until the operation is com- pleted.
  • Page 143 tentative TMP86FH09NG 14.4 Access to the Flash Memory Area When the write, erase and read protections are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. Therefore, to perform these operations in the entire flash memory area, access to the flash memory area by the control program in the BOOTROM or RAM area.
  • Page 144 tentative 14. Flash Memory 14.4 Access to the Flash Memory Area TMP86FH09NG Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H. : Disable interrupts (IMF←"0") (FLSCR),0011_1000B : Enable command sequence execution. IX,0F555H IY,0FAAAH HL,0F000H ;...
  • Page 145 tentative TMP86FH09NG 14.4.2 Flash Memory Control in the MCU mode In the MCU mode, write operations are performed by executing the control program in the RAM area. Before execution of the control program, copy the control program into the RAM area or obtain it from the external using the communication pin.
  • Page 146 tentative 14. Flash Memory 14.4 Access to the Flash Memory Area TMP86FH09NG Example :After sector erasure (E000H-EFFFH), the program in the RAM area writes data 3FH to address E000H. : Disable interrupts (IMF←"0") (WDTCR2),4EH : Clear the WDT binary counter. (WDTCR1),0B101H : Disable the WDT.
  • Page 147 tentative TMP86FH09NG 15. Serial PROM Mode 15.1 Outline The TMP86FH09NG has a 2048 byte BOOTROM (Mask ROM) for programming to flash memory. The BOOTROM is available in the serial PROM mode, and controlled by TEST, BOOT and pins. Communica- RESET tion is performed via UART.
  • Page 148 tentative 15. Serial PROM Mode 15.3 Serial PROM Mode Setting TMP86FH09NG 15.3 Serial PROM Mode Setting 15.3.1 Serial PROM Mode Control Pins To execute on-board programming, activate the serial PROM mode. Table 15-2 shows pin setting to activate the serial PROM mode. Table 15-2 Serial PROM Mode Setting Setting TEST pin...
  • Page 149 tentative TMP86FH09NG TMP86FH09NG VDD(4.75 V to 5.25 V) Serial PROM mode TEST MCU mode pull-up BOOT / RXD (P02) TXD (P03) XOUT External control RESET Figure 15-2 Serial PROM Mode Pin Setting Note 1: For connection of other pins, refer to " Table 15-3 Pin Function in the Serial PROM Mode ". 15.3.3 Example Connection for On-Board Writing Figure 15-3 shows an example connection to perform on-board wring.
  • Page 150 tentative 15. Serial PROM Mode 15.3 Serial PROM Mode Setting TMP86FH09NG 15.3.4 Activating the Serial PROM Mode The following is a procedure to activate the serial PROM mode. " Figure 15-4 Serial PROM Mode Timing " shows a serial PROM mode timing. 1.
  • Page 151 tentative TMP86FH09NG 15.4 Interface Specifications for UART The following shows the UART communication format used in the serial PROM mode. To perform on-board programming, the communication format of the write controller must also be set in the same manner. The default baud rate is 9600 bps regardless of operating frequency of the microcontroller. The baud rate can be modified by transmitting the baud rate modification data shown in Table 1-4 to TMP86FH09NG.
  • Page 152 tentative 15. Serial PROM Mode 15.4 Interface Specifications for UART TMP86FH09NG Table 15-5 Operating Frequency and Baud Rate in the Serial PROM Mode Reference Baud Rate 76800 62500 57600 38400 31250 19200 9600 (bps) Baud Rate Modification (Note 3) Data Ref.
  • Page 153 tentative TMP86FH09NG 15.5 Operation Command The eight commands shown in Table 15-6 are used in the serial PROM mode. After reset release, the TMP86FH09NG waits for the matching data (5AH). Table 15-6 Operation Command in the Serial PROM Mode Command Data Operating Mode Description Setup...
  • Page 154 tentative 15. Serial PROM Mode 15.6 Operation Mode TMP86FH09NG 6. Flash memory status output mode The status of the area from FFE0H to FFFFH, and the read protection condition are output as 7-byte code. The external controller reads this code to recognize the flash memory status. 7.
  • Page 155 tentative TMP86FH09NG 15.6.1 Flash Memory Erasing Mode (Operating command: F0H) Table 15-7 shows the flash memory erasing mode. Table 15-7 Flash Memory Erasing Mode Transfer Data from the External Transfer Data from TMP86FH09NG to the Transfer Byte Baud Rate Controller to TMP86FH09NG External Controller 1st byte Matching data (5AH)
  • Page 156 tentative 15. Serial PROM Mode 15.6 Operation Mode TMP86FH09NG 2. The 5th byte of the received data contains the command data in the flash memory erasing mode (F0H). 3. When the 5th byte of the received data contains the operation command data shown in Table 15-6, the device echoes back the value which is the same data in the 6th byte position of the received data (in this case, F0H).
  • Page 157 tentative TMP86FH09NG 15.6.2 Flash Memory Writing Mode (Operation command: 30H) Table 15-8 shows flash memory writing mode process. Table 15-8 Flash Memory Writing Mode Process Transfer Data from External Controller Transfer Data from TMP86FH09NG to Transfer Byte Baud Rate to TMP86FH09NG External Controller 1st byte Matching data (5Ah)
  • Page 158 tentative 15. Serial PROM Mode 15.6 Operation Mode TMP86FH09NG Description of the flash memory writing mode 1. The 1st byte of the received data contains the matching data. When the serial PROM mode is acti- vated, TMP86FH09NG (hereafter called device), waits to receive the matching data (5AH). Upon reception of the matching data, the device automatically adjusts the UART’s initial baud rate to 9600 bps.
  • Page 159 tentative TMP86FH09NG record, the external controller judges whether the transmission is completed correctly by receiving the checksum sent by the device. 14. After transmitting the checksum, the device waits for the next operation command data. Note 1: Do not write only the address from FFE0H to FFFFH when all flash memory data is the same. If only these area are written, the subsequent operation can not be executed due to password error.
  • Page 160 tentative 15. Serial PROM Mode 15.6 Operation Mode TMP86FH09NG 15.6.3 RAM Loader Mode (Operation Command: 60H) Table 15-9 shows RAM loader mode process. Table 15-9 RAM Loader Mode Process Transfer Data from External Control- Transfer Data from TMP86FH09NG to Transfer Bytes Baud Rate ler to TMP86FH09NG External Controller...
  • Page 161 tentative TMP86FH09NG Note 8: If an error occurs during the reception of a password address or a password string, TMP86FH09NG stops UART commu- nication and enters the halt condition. In this case, initialize TMP86FH09NG by the pin and reactivate the serial RESET PROM mode.
  • Page 162 tentative 15. Serial PROM Mode 15.6 Operation Mode TMP86FH09NG 15.6.4 Flash Memory SUM Output Mode (Operation Command: 90H) Table 15-10 shows flash memory SUM output mode process. Table 15-10 Flash Memory SUM Output Process Transfer Data from External Control- Transfer Data from TMP86FH09NG to Transfer Bytes Baud Rate ler to TMP86FH09NG...
  • Page 163 tentative TMP86FH09NG 15.6.5 Product ID Code Output Mode (Operation Command: C0H) Table 15-11 shows product ID code output mode process. Table 15-11 Product ID Code Output Process Transfer Data from External Controller Transfer Data from TMP86FH09NG to Transfer Bytes Baud Rate to TMP86FH09NG External Controller 1st byte...
  • Page 164 tentative 15. Serial PROM Mode 15.6 Operation Mode TMP86FH09NG 5. After sending the checksum, the device waits for the next operation command data. Page 164...
  • Page 165 tentative TMP86FH09NG 15.6.6 Flash Memory Status Output Mode (Operation Command: C3H) Table 15-12 shows Flash memory status output mode process. Table 15-12 Flash Memory Status Output Mode Process Transfer Data from External Con- Transfer Data from TMP86FH09NG to Exter- Transfer Bytes Baud Rate troller to TMP86FH09NG nal Controller...
  • Page 166 tentative 15. Serial PROM Mode 15.6 Operation Mode TMP86FH09NG 15.6.7 Flash Memory Read Protection Setting Mode (Operation Command: FAH) Table 15-13 shows Flash memory read protection setting mode process. Table 15-13 Flash Memory Read Protection Setting Mode Process Transfer Data from External Con- Transfer Data from TMP86FH09NG to Exter- Transfer Bytes Baud Rate...
  • Page 167 tentative TMP86FH09NG this case, FAH). If the 5th byte does not contain the operation command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63H). 4. The 7th through m’th bytes of the transmitted and received data contain the same data as in the flash memory writing mode.
  • Page 168 tentative 15. Serial PROM Mode 15.7 Error Code TMP86FH09NG 15.7 Error Code When detecting an error, the device transmits the error code to the external controller, as shown in Table 15-14. Table 15-14 Error Code Transmit Data Meaning of Error Data 62H, 62H, 62H Baud rate modification error.
  • Page 169 tentative TMP86FH09NG 15.8.2 Calculation data The data used to calculate the checksum is listed in Table 15-15. Table 15-15 Checksum Calculation Data Operating Mode Calculation Data Description Even when a part of the flash memory is written, the checksum Flash memory writing mode of the entire flash memory area (C000H to FFFH) is calcu- Data in the entire area of the flash memory lated.
  • Page 170 tentative 15. Serial PROM Mode 15.9 Intel Hex Format (Binary) TMP86FH09NG 15.9 Intel Hex Format (Binary) 1. After receiving the checksum of a data record, the device waits for the start mark (3AH “:”) of the next data record. After receiving the checksum of a data record, the device ignores the data except 3AH transmitted by the external controller.
  • Page 171 tentative TMP86FH09NG RXD pin UART F0H 12H F1H 07H 01H 02H 03H 04H 05H 06H 07H 08H Password string PNSA PCSA Flash memory F012H "08H" becomes the umber of Compare passwords F107H F108H F109H F10AH 8 bytes F10BH F10CH Example PNSA = F012H F10DH PCSA = F107H...
  • Page 172 tentative 15. Serial PROM Mode 15.11 Product ID Code TMP86FH09NG 15.11Product ID Code The product ID code is the 13-byte data containing the start address and the end address of ROM. Table 15-17 shows the product ID code format. Table 15-17 Product ID Code Format Data Description In the Case of TMP86FH09NG...
  • Page 173 tentative TMP86FH09NG Flash memory read pro- Read protection is disabled. RPENA tection status Read protection is enabled. The status from FFE0H All data is FFH in the area from FFE0H to FFFFH. BLANK to FFFFH. The value except FFH is included in the area from FFE0H to FFFFH. Some operation commands are limited by the flash memory status code 1.
  • Page 174 tentative 15. Serial PROM Mode 15.13 Specifying the Erasure Area TMP86FH09NG 15.13Specifying the Erasure Area In the flash memory erasing mode, the erasure area of the flash memory is specified by n−2 byte data. The start address of an erasure area is specified by ERASTA, and the end address is specified by ERAEND. If ERASTA is equal to or smaller than ERAEND, the sector erase (erasure in 4 kbyte units) is executed.
  • Page 175 tentative TMP86FH09NG Port Input Control Register SPCR (0FEAH) (Initial value: **** ***0) Port input control in the serial PROM 0 : Invalid port inputs (The input level is fixed with a hardware feature.) mode 1 : Valid port inputs Note 1: The SPCR register can be read or written only in the serial PROM mode. When the write instruction is executed to the SPCR register in the MCU mode, the port input control can not be performed.
  • Page 176 tentative 15. Serial PROM Mode 15.15 Flowchart TMP86FH09NG 15.15Flowchart Page 176...
  • Page 177 tentative TMP86FH09NG 15.16UART Timing Table 15-19 UART Timing-1 (VDD = 4.75 to 5.25 V, fc = 2 to 16 MHz, Topr = -10 to 40°C) Minimum Required Time Parameter Symbol Clock Frequency (fc) At fc = 2 MHz At fc = 16 MHz 465 µs 58.1 µs Time from matching data reception to the echo back...
  • Page 178 tentative 15. Serial PROM Mode 15.16 UART Timing TMP86FH09NG Page 178...
  • Page 179 tentative TMP86FH09NG 16. Input/Output Circuitry 16.1 Control Pins The input/output circuitries of the TMP86FH09NG control pins are shown below. Control Pin Input/Output Circuitry Remarks Osc.enable Resonator connecting pins Input = 1.55 MΩ (typ.) XOUT Output = 0.5 kΩ (typ.) XOUT XTEN Osc.enable Resonator connecting pins...
  • Page 180 tentative 16. Input/Output Circuitry 16.2 Input/Output Ports TMP86FH09NG 16.2 Input/Output Ports Control Pin Input/Output Circuitry Remarks Initial "High-Z" Sink open drain output Pch control Data output Push-Pull output Input from output latch Hysteresis input High current output(Nch) High-Z control (Programmable port option) Pin input Initial "High-Z"...
  • Page 181 tentative TMP86FH09NG 17. Electrical Characteristics 17.1 Absolute Maximum Ratings The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user.
  • Page 182 tentative 17. Electrical Characteristics 17.1 Absolute Maximum Ratings TMP86FH09NG 17.2 Recommended Operating Conditions The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur.
  • Page 183 tentative TMP86FH09NG 17.2.3 Serial PROM mode = 0 V, Topr = -10 to 40 °C) Parameter Symbol Pins Condition Unit Supply voltage NORMAL1, 2 modes 4.75 5.25 × 0.70 Except hysteresis input ≥ 4.75 V Input high voltage × 0.75 Hysteresis input ×...
  • Page 184 tentative 17. Electrical Characteristics 17.1 Absolute Maximum Ratings TMP86FH09NG 17.3 DC Characteristics = 0 V, Topr = -40 to 85 °C) Parameter Symbol Pins Condition Typ. Unit Hysteresis voltage Hysteresis input – – TEST = 5.5 V, V = 5.5 V/0 V µA Input current Sink open drain, tri–state port...
  • Page 185 tentative TMP86FH09NG 17.4 AD Characteristics = 0.0 V, 4.5 V ≤ V ≤ 5.5 V, Topr = -40 to 85 °C) Paramete Symbol Condition Typ. Unit Analog input voltage – Non linearity error – – T.B.D Zero point error – –...
  • Page 186 tentative 17. Electrical Characteristics 17.6 Flash Characteristics TMP86FH09NG 17.5 AC Characteristics = 0 V, 4.5 V ≤ V ≤ 5.5 V, Topr = -40 to 85°C) Parameter Symbol Condition Typ. Unit NORMAL1, 2 modes 0.25 – IDLE0, 1, 2 modes µs Machine cycle time SLOW1, 2 modes...
  • Page 187 tentative TMP86FH09NG 17.7 Recommended Oscillating Conditions XTOUT XOUT XTIN (1) High-frequency Oscillation (2) Low-frequency Oscillation Note 1: To ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. Because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted.
  • Page 188 tentative 17. Electrical Characteristics 17.6 Flash Characteristics TMP86FH09NG 17.8 Handling Precaution - The solderability test conditions for lead-free products (indicated by the suffix G in product name) are shown below. 1. When using the Sn-63Pb solder bath Solder bath temperature = 230 °C Dipping time = 5 seconds Number of times = once R-type flux used...
  • Page 189 tentative TMP86FH09NG 18. Package Dimension P-SDIP32-400-1.78 Unit: mm Page 189...
  • Page 190 tentative 18. Package Dimension TMP86FH09NG Page 190...
  • Page 191 This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). Toshiba provides a variety of development tools and basic software to enable efficient software development. These development tools have specifications that support advances in microcomputer hardware (LSI) and can be used extensively.

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